USB superspeed peripherals Forum Discussions
HI this is @clinton
I am generating the pwm wave in gpio 50 as a complex mode with cx3 rdk so i have an issue with this
i want to switch from complex to simple when duty cycle is zero i used overide api with correct parameters
the override function also worked . so problem is when duty cycle is zero I am changing the gpio to simple and set the value to zero but its not work in osciloscope its reflecting with 1 percent duty cycle and same in 100 perecent duty cycle also its showing around 99 percent can any one have any idea??
i am doing somewhere wrong i thinks guide me to reach the endpoint
Best Regards
clinton
Show LessHi, community
I've read this thread https://community.infineon.com/t5/USB-superspeed-peripherals/How-to-fill-in-the-timestamp-of-UVC-payload-header/td-p/279557, but still have confusions on the implement
-
PTS: As the UVC 1.5 spec mentioned "The source clock time in native device clock units when the raw frame capture". How to get the time on the capture begins exactly? Via monitoring the state of the GPIF SM?
- STC: "STC must be captured when the first video data of a video frame is put on the USB bus". is it the timestamp when the first packet of the frame is committed to the USB bus?
-
1KHz SOF token counter: Should I just use the lower 11bit of the glFrameCount?
Regards
Rossi
Show Less
Hi all,
I'm using fX3s to receive data that is being pushed from the Host PC. And I have created the DMA Auto Signal channel with 25 buffers each of size 8K. The data that is being pushed at the Host PC side is not fixed, it varies from 256byte to 8k. When I have the larger data length, data rate is as expected. But when the data length is less, data rate is very less.
Currently i'm using the below code piece to push data from Host PC.
retVal = Endpt->XferData(data, len);
if (!retVal)
{
Endpt->Abort();
Endpt->Reset();
}
Now my questions are,
1. Is there any better way to push data at Host PC, which improves the data rate.?
2. Why such behaviour for data with small size?
3. Is there any C/C++ example code for data push from Host PC to cypress?
NOTE: i'm using C++ application at Host side.
Please help me out to solve the problem.
Thanks & Regards
Yamuna G
Show Less
Hello @AliAsgar I want to generate a pwm wave form with varrying frequency and varrying duty cyclei made nesseccary changes for that can you please let me know what silly mistake i making
while i am varrying brightness control the frequency is varrying in oscliscope but when i change contrast control its not changing why its happen like that
I taken period =2016000 for 100hz and multiplying that
I also have bit confusion one how to take apropirate value in period for correct frequency and what value we have to take for the correct duty cycle thank you
Hi,
we are using an example code "UsbSpiGpioMode", from FX3 SDK 1.3 and verified a few transactions(Read, Write, and Erase) in the CX3 Denebola Eval board using the Control Center utility. When trying to erase the page in SPI Flash memory, an error occurred as "CONTROL OUT transfer failed with Error Code:997".
Detail info:
1. Write to SPI flash - working
2. Read from SPI flash - working
3. Erase SPI flash sector - CONTROL OUT transfer failed with
Error Code:997
The only download I can find for the GPIF Designer is the GPIF Designer (1) which clearly is not the GPIF II Designer.
https://www.infineon.com/cms/en/design-support/tools/configuration/usb-gpif-designer/
The screenshots in the GPIF II Designer do not match the appearance of the program I can download currently via the above link (Infineon-gpif_designer_13-Software-v01_00-EN.zip).
I am not able to modify my device's GPIF II configuration at the present.
Show LessI'm designing a board with an Efinix FPGA which includes a RISC-V processor running linux. I would like to use an fx3 as a host controller talking to the processor. In order to do this I need a linux usb host driver. I can easily attach the SRAM interface of the fx3 to the AXI4 bus of the RISC-V processor and do any address mapping as needed (advantage of having an FPGA)
Since the fx3 has EHCI registers this seems like something that could be done, but I have searched and searched and cannot find anything. I downloaded the fx3 SDK and could not find anything in there for a linux host driver. Does such a thing exist?
Of course I will also need firmware in the fx3 for this, I presume that is implemented with host API calls. It would be nice if there was already something that does this, or at least someplace to start.
The FPGA eval board already includes an fx3 connected to a bunch of pins of the FPGA which seems to be compatible with the SRAM interface so with the proper linux host driver this should work.
Any hints on if anything exists or some pointers on how to get started implementing this if nothing exists would be greatly appreciated.
John S.
Show LessHi,
Guide me on how to flash Bootloader sw into CX3/ SPI Flash memory. Since, we could not directly use USB for this purpose which need USB descriptor for communicate.
we would try to use JTAG pins initially to flash bootload code into memory and afterwards we will use Bootloader to work remaining. Is there any example code available?
1. For Custom CX3 IC, is ready Bootloader available in CX3 chip itself?
2. Once bootloader code flashed, Does CX3 be used in Control center for Flashing main code as we are doing the same using Evaluation board?
Show LessHi,
How do configure/code to make a thread into sleep mode and how do wake up from sleep mode to an active mode without affecting other threads? its not like cyclic.
the use case is,
(Considering GPIOAPP Example code as a reference)
During video streaming in UVC(active thread), the GPIO thread will be in a sleep state and whenever a GPIO Event(Button press) is received, the GPIO thread will wake up to blink the LED and again goes to a sleep state.
Or, is it possible on putting the GPIO thread in non-cyclic mode?
How can I force FX3 to run in USB 3.0? If it can't run in USB 3.0, doesn't run in USB 2.0.
Regards,
Kyle