USB superspeed peripherals Forum Discussions
I am using CYUSB3KIT-003 and the CYUSB3ACC-005 to work with Xilinx ZC702 to stream video into PC.
I realize the FPGA serves as a master role in the GPIF port.
I am reading the AN65974 but how does the GPIF communicate to the FPGA how many bytes the PC has or wants?
How do the control packets get into the FPGA?
Show LessI have the EZ-USB FX3 DVK. I am trying to debug it using the Cypress EZ USB Suite, and an Olimex ARM-USB-OCD-H.
I followed the instructions in the EZ-USB Suite Users Guide for using OpenOCD to debug. When ever I try to debug in the IDE I recieve the following error:
Open On-Chip Debugger 0.8.0 (2014-12-03-15:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : Adapter driver 'cy7c65215' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 1000 kHz
trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull srst_open_drain connect_deassert_srst
RCLK - adaptive
adapter speed: 1000 kHz
Error: CyJtagDevice Not found
in procedure 'init'
This is followed by:
Quit (expect signal SIGINT when the program is resumed)
Quit (expect signal SIGINT when the program is resumed)
Quit (expect signal SIGINT when the program is resumed)
Exception condition detected on fd 0
error detected on stdin
I've tried using a different config file, which I found on this site, and using the Olimex supplied openocd.exe, but nothing seems to work.
Can anyone help me out with this? I'm running out of ideas.
Show LessHi.
I ran across as below code to control i2c with Omnivision sensor(The device slave addresses are 0x78 for write and 0x79 for read.).
/* Functions for OmniVision Chips */
void sccb_read_reg(uint8_t reg, uint8_t *data)
{
CyU3PReturnStatus_t apiRetStatus;
CyU3PI2cPreamble_t preamble;
preamble.buffer[0] = 0x60;
preamble.buffer[1] = reg;
preamble.buffer[2] = 0x61;
preamble.length = 3;
preamble.ctrlMask = 1 << 1;
apiRetStatus = CyU3PI2cReceiveBytes(&preamble, data, 1, 0);
if(apiRetStatus != CY_U3P_SUCCESS){
CyU3PDebugPrint(8, "i2c Receive Failed, Error Code = %d\n\r", apiRetStatus);
}else{
CyU3PDebugPrint(8, "i2c Receive Data = %x,%x\n\r", reg, *data);
}
}
void sccb_write_reg(uint8_t reg, uint8_t *data)
{
CyU3PReturnStatus_t apiRetStatus;
CyU3PI2cPreamble_t preamble;
preamble.buffer[0] = 0x60;
preamble.buffer[1] = reg;
preamble.length = 2;
preamble.ctrlMask = 0 << 2;
apiRetStatus = CyU3PI2cTransmitBytes(&preamble, data, 1, 0);
if(apiRetStatus != CY_U3P_SUCCESS){
CyU3PDebugPrint(8, "i2c Send Failed, Error Code = %d\n\r", apiRetStatus);
}else{
CyU3PDebugPrint(8, "i2c Send Data = %x,%x\n\r", reg, *data);
}
}
Also i found this code envolved in cyu3i2c.c. But I can't found how to implement and use this function.
Because It doesn't work when I used that, There is any response from SCL,SDA lines. can you let me know how to use this function with example?
below is my snippet code.
void sccb_read_reg(uint8_t reg, uint8_t *data)
{
CyU3PReturnStatus_t apiRetStatus;
CyU3PI2cPreamble_t preamble;
preamble.buffer[0] = 0x42;
preamble.buffer[1] = reg;
preamble.buffer[2] = 0x43;
preamble.length = 3;
preamble.ctrlMask = 1 << 1;
apiRetStatus = CyU3PI2cReceiveBytes(&preamble, data, 1, 0);
if(apiRetStatus != CY_U3P_SUCCESS){
CyU3PDebugPrint(8, "i2c Receive Failed, Error Code = %d\n\r", apiRetStatus);
}else{
CyU3PDebugPrint(8, "i2c Receive Data = %x,%x\n\r", reg, *data);
}
}
void sccb_write_reg(uint8_t reg, uint8_t *data)
{
CyU3PReturnStatus_t apiRetStatus;
CyU3PI2cPreamble_t preamble;
preamble.buffer[0] = 0x42;
preamble.buffer[1] = reg;
preamble.length = 2;
preamble.ctrlMask = 0 << 2;
apiRetStatus = CyU3PI2cTransmitBytes(&preamble, data, 1, 0);
if(apiRetStatus != CY_U3P_SUCCESS){
CyU3PDebugPrint(8, "i2c Send Failed, Error Code = %d\n\r", apiRetStatus);
}else{
CyU3PDebugPrint(8, "i2c Send Data = %x,%x\n\r", reg, *data);
}
}
CyBool_t
CyFxSlFifoApplnUSBSetupCB (
uint32_t setupdat0,
uint32_t setupdat1
)
{
/* Fast enumeration is used. Only requests addressed to the interface, class,
* vendor and unknown control requests are received by this function.
* This application does not support any class or vendor requests. */
uint8_t bRequest, bReqType;
uint8_t bType, bTarget;
uint16_t wValue, wIndex, wLength;////
CyBool_t isHandled = CyFalse;
///////
//uint16_t temp;
//CyU3PReturnStatus_t status;
/////
/* Decode the fields from the setup request. */
bReqType = (setupdat0 & CY_U3P_USB_REQUEST_TYPE_MASK);
bType = (bReqType & CY_U3P_USB_TYPE_MASK);
bTarget = (bReqType & CY_U3P_USB_TARGET_MASK);
bRequest = ((setupdat0 & CY_U3P_USB_REQUEST_MASK) >> CY_U3P_USB_REQUEST_POS);
wValue = ((setupdat0 & CY_U3P_USB_VALUE_MASK) >> CY_U3P_USB_VALUE_POS);
wIndex = ((setupdat1 & CY_U3P_USB_INDEX_MASK) >> CY_U3P_USB_INDEX_POS);
/////////////
uint8_t i2cAddr;
/////////////
wLength = ((setupdat1 & CY_U3P_USB_LENGTH_MASK) >> CY_U3P_USB_LENGTH_POS);
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
/////////////////////
if (bType == CY_U3P_USB_VENDOR_RQT)
{
/* Vendor command is sent by test applications. Start the loop that tries to keep the link
* in U0.
*/
gDoLpmDisable = CyTrue;
switch (bRequest)
{
........
........
///////////////////////////////////////
case CY_FX_RQT_I2C_EEPROM_WRITE: //0xBA
i2cAddr = 0x21 | ((wValue & 0x0007) << 1);
status = CyU3PUsbGetEP0Data(wLength, glEp0Buffer, NULL);
if (status == CY_U3P_SUCCESS)
{
CyFxUsbI2cTransfer (wIndex, i2cAddr, wLength,
glEp0Buffer, CyFalse);
}
break;
case CY_FX_RQT_I2C_EEPROM_READ: //0xBB
sccb_read_reg((uint8_t)wValue, glEp0Buffer);
I'm not sure what am I wrong. I just received error message "i2c Receive Failed, Error Code = 68 ". what am I supposed to do for solving this problem?
And I have another question. basically Omnivision address register size consisted with 1 word size not 1 byte such as 0x3000..0x4301...,.. So i'd like to control with word size. what am I supposed to make a handle this?
Thanks for in advanced.
Show LessHi there,
We are currently using the FX3 reference design and like it very much as a device.
Another product of ours calls for a hub functionality, so that means we should use the HX3 for that (are there other Cypress options?).
We would like to modify the firmware on the HX3 so that we can:
1. change the routing of packets:
a. e.g. a packet destined to port 1, send it to port 3 instead,
b. dump packets, based on their contents (e.g. packets sent from a device to our "hub").
2. report device connect/disconnect (on the status change endpoint).
Is it possible to do that with the HX3?
What SDK do I use for that?
BTW: I understand there are 16KB RAM on the HX3 boards. It does not include the USB buffers, right?
If so, how big are the HW buffers on those reference boards?
Thanks,
Show LessI used the cyusb3014 communication with FPGA(V-series of Xilinx) and there is no problems. But, now I use the chip of XILINX(K-series) to transfer data with PC,there is some problems. When I connect the USB data line with PC, there is the drive(named Cypress USB Bootloader) . After I download the bit file of my project ,the drive(named Cypress USB Bootloader) is dropped, not become the Cypress USB SreammerExample.
I don't know why!
Surely it doesn't mean that because the K-series of XILINX? I don't think so . But why?
Does anyone ever meet this issue ?Is there any explanation to that ?
Thanks for any returns
Show LessHi,Sir!
I want to output PWM signal to drive LED brightness, which gpio can be used as PWM output and how to initialize the pwm registers?
Where can I download the detailed specification about GPIO,timer,PWM, intterrupt.
David
Show LessI have a question with regard to the GPIF II Designer:
I am trying to create a simple local bus interface where the FX3 is the master and have noticed that whenever I describe a group of states to perform a read of a slave that the IN_DATA action appears to want the data bus to be driven by the slave at least 1 state early if not 2 depending on how you want to look at it. The attached jpg file is a screen shot of the timing diagram created by GPIF II Designer and in the state machine IN_DATA is an action in the FIFO_RD_1ST state. I wouldn't expect the data to have to be valid until at least that state if not the one after depending on how IN_DATA is treated.
I don't have a software resource available yet or I would just try it to find out the answer. At this point I am just trying to charcterize the interface to see what is possible and how best to utilize the FX3 in our designs.
Show LessWe have designed a system using FX3 and this system is two asynchronous combination with Master (FX3) and Slave (FPGA) .
Slave (FPGA) is a very passive device, must Master (FX3) transmission inform reception to Slave(FPGA) and FPGA to be able to send data to 16Bits DataBus and let FX3 reception.
As described in an uploaded image file(Image 1), we can see there are three groups of signal lines. There are sent from the Master Control pin RD, Slave reception state pin WAIT and 16Bits DataBus. Because there is no common use Master Clk, so this is a two asynchronous design concept.
As shown in image file(Image 1), the expected timing diagram for the planning of the system, as shown in Figure (Image 2) to see, RD and WAIT pin initial state are keep High. When the time arrives when T2, Master requires the ability to RD Pin tie Low,in order to told the Slave side Master want to collect the data(Master must have the ability to control receive/not receive).
After RD Tie Low,Slave discovery will begin to prepare data , when the time reaches T3, Slave ready DataBus on good Data, and the WAIT tie Low told the Master can receive data on the Data Bus,When T4 after time, Master charged DataBus data on completed, it will represent RD tie High data collection has been completed, the T5 when the time arrives,Slave discovery RD tie High, Slave will know Master has the right to receive data, and will then WAIT tie High complete the transfer once time.
To start the next, Master send data will first confirm whether the High WAIT, if continue to take a High data transmission,Otherwise, wait until the Slave WAIT pin tie High.
The question is, as I refer to Cypress GPIF II offer an example, most of the examples of receiving the information in the USB,Through a Slave is from the end (FPGA or others MCU) additional GPIO Pin to inform FX3, let FX3 to perform reception work,Does not seem a way to make the PC side can place an order requires the receiving FPGA information, FX3 will go in front of the execution timing of drawing 2 above.
We have thought about of reference "DMA_RDY_TH1" to complete, when DMA_RDY_TH1 = true, executes the reception process (such as shown in Image 2), but this is not what we want, We hope to make the client has control over the PC, We hope to make the client has control over the PC, not observed FX35 DMA_RDY_TH1 state and then decide whether to execute the process of receiving information.
therefore~
Question 1: Do you have an example of what can make the PC side have mastership, when PC client requests received, FX3 able to perform drawing two receiving process described?
Question 2: Do you have to help the team responsible for solving engineering problems or FAE right here in Taiwan?
Thank you..
Show LessI'm face to priority when I want to use in parallel 2 EPIN: One is transferring high speed data from GPIF to USB, the other low speed data from UART to USB. Both of them are connected to DMA AUTO but the UART has and AUTO SIGNAL allowing to set a flag (_pktsPendingUart) when a transfer is completed. Within a thread, I read the flag every 40ms and if not set I use the CyU3PDmaChannelSetWrapUp() in order to tell to USB they might be some bytes in the DMA buffer so the host can get it with XferData().
The thing is while the GPIF to USB is sending some data to the host, the DMA UART wrapup or the associated EPIN is stuck since I don't see anymore UART Data Packet on the USB and any XferData() call returns LastError/NtStatus/UsbdStatus = 997/995/0xC001000 on the 1st call and then 997/23/0xC0000011 on the next calls
So I wonder how to suspend the GPIF DMA, force the UART DMA and resume the GPIF in the thread body, something like the code below, BUT IT DOESN'T WORK. Any other method or do I use these functions correctly ?
while(true){
if (_pktsPendingUart == 0){
CyU3PDmaChannelSetSuspend(&_glChHandleSlFifoGPIFtoUSB, CY_U3P_DMA_SCK_SUSP_NONE, CY_U3P_DMA_SCK_SUSP_EOP);
CyU3PDmaChannelSetWrapUp (&_glChHandleUarttoUsb);
CyU3PDmaChannelSetSuspend(&_glChHandleSlFifoGPIFtoUSB, CY_U3P_DMA_SCK_SUSP_NONE, CY_U3P_DMA_SCK_SUSP_NONE);
CyU3PDmaChannelResume(&_glChHandleSlFifoGPIFtoUSB, CyTrue, CyTrue);
}//end if
_pktsPendingUart = 0;
CyU3PThreadSleep (40);
}//end while
PS : I've also tried CY_U3P_DMA_SCK_SUSP_CUR_BUF and CY_U3P_DMA_SCK_SUSP_CONS_PARTIAL_BUF rather than CY_U3P_DMA_SCK_SUSP_EOP but nothing is working.
Show LessHello- I hope this is the correct forum for this if not please point me to the right place....
I have a simple EZ-USB Suite project for the FX3 created on a Win 7- it builds fine. When I try and bring the project over to a Win10 machine, clicking the Build Project button tells me there is 'Nothing To Build' . Looking at the Tool Chain Editor settings, I see the following error under the Configuration setting:
Orphaned configuration. No base extension cfg exists for ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1524826368
Under Current toolchain, I see
Orphaned toolchain ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.402899216 (Cross ARM GCC)
And under Current builder I see
Orphaned builder ilg.gnuarmeclipse.managedbuild.cross.builder.1857435584 (Gnu Make Builder)
Try as I might I can not seem to fix this. Searching around indicates something about wrong plugins being installed but if I try and 'Install New Software' I do not get any options to install. This is happening on 2 different Win 10 machines after a clean install of the FX3 SDK and Dev Kit tools. The attached doc shows the Tool Chain dialogue.
Thanks for any help you can provide.
Show Less