USB superspeed peripherals Forum Discussions
text.format{('custom.tabs.no.results')}
The image is part of my state machine, the data bus is 32 bits. When watermark is set to 1 4-bytes-word, the state machine works well. In this case, the GPIF can continuously transfer data to DMA with no data loss.
So, my previous topic on this matter got locked after receiving some replies by someone who clearly does not speak English.
The problem is still same.
1. FX3 SDK comes as a .exe installer. WHY? It's a freaking SDK. Offer it as a zip file, developers know what to do with it.
2. FX3 SDK 1.3.5 Requires .NET 3.5 which is at this point nearly 20 years old and does not come with any new computer.
How I know?
Simple.
1. Download ezusbfx3sdk_1.3.5_Windows_x32-x64.exe
2. Run it on Windows 10 (Which comes with .NET Framework 4.7 or 4.8 or whatever, something recent)
3. Receive the following error:
---------------------------
Setup
---------------------------
FX3 SDK requires Microsoft .NET Framework 3.5 or above. Please use Windows Update to install this version, and then re-run the FX3 SDK setup.
---------------------------
OK
---------------------------
I have no idea why previous thread kept asking for "please share the error log and screenshot if you get any while installing sdk 1.3.5."
This is literally the error message right there. "requires net 3.5"
When installing on Windows 10 which already HAS .NET 4.xx
If you're going to say 'but it needs .NET SDK or something' but guess what, this same machine I just ran the installer on has Visual Studio 2022 installed with C# development AND of course, .NET SDK.
The real problem is installer (not necessary) and broken installer (incorrect check for ancient .NET version).
Can someone who can actually read and understand English reply to this post with something that makes sense? Thanks!
Show Less
hello.
What is the latest driver version for fx3 USB and where can I get it?
We are reviewing 100-ball BGA package - HX3 schemaitc and refer to HX3 Hardware Design Guidelines and Schematic Checklist application note,
the application note notices that "For the 1.2-V power supply, as shown in Figure 2, a ferrite bead is required
to isolate the noisy power supply (1.2-V core supply) from the domains that need clean power supply (1.2 V for SS Rx, Tx and crystal oscillator)"
but datasheet and application note don't explain which pins of 100-ball BGA package are "1.2V for core" and which pins are "1.2V for SS TX".
Do you have documentation to explain?
Show Less
Hi
I am a FPGA developer.
Currently I am interfacing my artix7 100t FPGA with fx3 controller having slave fifo.
Iam using streamin mode .
I am able to transfer 16384 bytes in a buffer.
But at some location data is not properly received From fx3 slave fifo
While transmitting my data at 100 mhz iam getting some loss after every 255 clock at my host end
Means on 1 st clock iam getting 1,
2nd clock iam getting 2
3 rd clock iam getting 3
4th clock Iam getting 4
.......
254th clock cycle Iam getting 254
255th clock cycle Iam getting 255
256th clock cycle Iam getting 16
257th clock cycle Iam getting 17
258th clock cycle Iam getting 18
259th clock cycle Iam getting 19
260th clock cycle Iam getting 20
261th clock cycle Iam getting 21
262th clock cycle Iam getting 22
263th clock cycle Iam getting 23
264th clock cycle
Iam getting 24
265th clock cycle Iam getting 25
266 th clock cycle Iam getting 266
267 th clock cycle Iam getting 267
268 th clock cycle Iam getting 268
.
I also tried to give constant value 256(fdata)
On write state on my streamin fsm (verilog)
At that time also I am getting 16.
Please let me know the issue and solution ?
Show Less
Hey all,
just a quick question about the 10-bit sampling for RAW10 and GPIO pin assignment for FX3 project. It's clear that for RAW8 we should connect GPIO[0:7] for sampling the sensor data, but in case for RAW10 with 6 bit padding, will we need GPIO[0:7] and in addition GPIO[8:9] or GPIO[14:15] so that no additional shifting is needed within software?
I would expect the following setup:
DQ[0] <- DVP[0]
...
DQ[7] <- DVP[7]
---------------------
DQ[8] <- DVP[8]
DQ[9] <- DVP[9]
DQ[10:15] <- NC
And how is the sampled bit order within the bytes of the DMA buffer? Will it be Pixel1 (DQ[15:8] | DQ[7:0]) ... PixelNth(DQ[15:8]|DQ[7:0]) or something else?
Hello,
I have modified the project usbuart from SDK with the below changes:
- added another 2 CDC interfaces, which makes the device detected as 2 virtual com port (VCP).
- The 1st VCP serves as the normal USB-UART bridge, which is the default behavior of the original project. After wiring up the UART TX/RX lines with an external MCU, this allows me to send the debug messages to that MCU in the 1st VCP, so does receive messages from the MCU.
- Messages shown in the 1st VCP can be obtained in the UART TX/RX lines from the logical analyzer.
- The 2nd VCP serves as the channel to debug messages to the FX3 chip itself. Whereases I create a MANUAL_IN dma channel between the UIB_PROD_5_SOCKET to the CPU_CONS_SOCKET to send message from host to FX3. And I call the function DebugInit( UIB_CONS_5_SOCKET) to print out messages to the 2nd VCP.
- The messages send/receive in the 2nd VCP will not affect the 1st VCP. In other words, messages shown in the 2nd VCP are not present on the FX3 UART lines.
Afterall, I tested my firmware on the CYUSB3KIT-003 dev board for FX3, and the firmware worked as expected. So far so good.
However, the same .img file does not work on the CX3 chip. I have tested on one of my customized board as well as on the Denebola dev board, and neither worked as expected. What I monitored are:
- the 1st VCP (USB-UART bridge) does not transfer the text sent in the serial terminal to the UART lines. I can not control the external MCU from the 1st VCP.
- the 2nd VCP worked fine. I am able to send and receive text in the serial terminal to the CX3 itself.
What could be the reason for that? Attached is the .img file works for the FX3 dev board. By sending text "test" to both VCP, you can identify the difference.
Thanks for your help.
Zhangshun
Show Less