USB superspeed peripherals Forum Discussions
What is the process to use DMA to transfer data to parallel bus from a CPU on FX3?
Already tried with success:
- USB socket to CPU interfaces using MANUAL_OUT and MANUAL_IN.
- Parallel Port Socket to USB socket interfaces using MANUAL operation.
- DMA fabric on the FX3 chip to accomplish a lot of high speed USB 3.0 transfers.
- DMA fabric to ping-pong outgoing DMA traffic to a USB endpoint similar to the UVC (AN75779) example.
- Slave Fifo example (AN65974) for the Xilink Spartan 7 board with a Super Speed Explorer board.
A CPU can be used to Commit the buffer and see the DMA Flags for the socket change.
Trying to read the parallel port socket, no data appears on the bus.
Why would this work differently than if a USB socket is initiating the DMA conversation in MANUAL?
Greg
Show LessHello,
We are looking into using the FX3 to connect up to 4 image sensors together using LVDS.
Each camera is potentially a 1 lane LVDS, grey scale 8 bit sensor with 640 x 480 resolution at 100 FPS, which is about 1 Gbps. This should in theory be low enough for USB3.1. Optimally we want to obtain 4 different images, but if that is not possible, one large combined image, which we can separate later our self is also acceptable.
It it possible LVDS-wise, to connect up to 4 sensors at this speed on the FX3?
At this point, is there any other complications that can be foreseen using this concept?
If there is another chip we are not aware of, which can do this, we are also interested in that.
Regards
Nicolai C.
Show LessI am driving the CX3 input by a MIPI video stream @2560x720p @25 fps (1 data lane, CSI clock @496MHz)
The MIPI stream is generated by a pair of sensors @1280x720p merged by a Lattice FPGA with mip2csi IP to get the CX3 input.
The configuration is successfully performed (with the obvious error that this will not work with USB 2.0) and the YVC CX3 is enumerated correctly. The FPGA is under debug so far ...
I am using the UVC Troubleshooting Guide – KBA226722 as a reference, still I would like to know in advance if the community can suggest if there are any issue
Thanks much
Show LessWhen debug the default USBBulkSourceSinkLED project, it takes 10-20 seconds to load the firmware to board, and printing messages like "Loading section *** ".
JTAG Speed is 1Mbps which can load 100KB of firmware in 1 second, what is the reason for this?
Show LessHi,
Currently, I am working with the CX3 code which was built in SDK 1.3.3 with CUStom GPIF to receive the data from the sensor. I want to use the inbuilt GPIF II to receive the data from the sensor using SDK 1.3.1. I had changed the project file as per the SDK 1.3.1 and I can able to build the code but I can't receive the data from the sensor.
Note: Sensor settings and CX3 receiver clock are perfect.
What are the things I need to be considered for these changes?
Thanks in advance.
Regards,
Esakki
Show LessIn figure 27 of "001-87216_AN87216_Designing_a_GPIF_II_Master_Interface.pdf", pin 5 of J6 is removed. In the schematics for that board, pin 5 of J6 is GND, the why is it removed? (There is no problem to remove it, but there seems to be no reason to remove it too)
Show LessHi,
I'm using CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit.
I connect it with my FPGA board and using asynslavefifo mode. my FPGA board continues to send data to the Kit by GPIO. I use either control center or my c++ GUI to receive data from it.The first 65536 16bit words are correct. but after that amount, All the data keep the value of last correct 16bit word.
for example: first word: FC 65
second word: EF 76
65536th: F0 19
then, from now on, all the data change to F0 19, F0 19, F0 19.......
after an even longer time, all the data changed to 00 00, 00 00,......
I tried either small frame(everytime transfer in a small amout of bytes like 1024, 4096 or 8192 ... but frame by frame continuously), or big frame(like 65536 , 131 072 or even bigger).
The result is the same.
in the firmware, DMA transfer size is set to infinite:
#define CY_FX_SLFIFO_DMA_TX_SIZE (0) /* DMA transfer size is set to infinite */
#define CY_FX_SLFIFO_DMA_RX_SIZE (0) /* DMA transfer size is set to infinite */
any one can help?
Thank
Zen
Show LessI use 4 MIPI CSI data lanes. What is frequency on MIPI CSI data lanes if MIPI CSI clock lane has 350MHZ? What is the calculation formula for this MIPI data lane frequency?
Show Less