USB superspeed peripherals Forum Discussions

Hello,

I am considering the CYUSB302x, CYUSB303x, CYUSB202x, for my project, but I would like to know the serial write performance when these devices are in MMC-DDR52 mode. So it is a High Speed mode , with Dual Data Rate in 52MHz. I would like to use 1 pin to transfert my data so the transfert will be serial.

Could you tell me what is this serial write performance ?

Regards

• Target: I want to transfer data from host to FPGA with CYUSB3014 in super speed mode.

• Implementation：win10

1.     Firmware: AN65974 with slavefifo2bit, endpoint 0x01 and 0x81, bulk mode,watermark = 6, FlagC and FlagD for 0x01 to transfer data from host to fpga
2. Verilog: fpga_master_streamIN_OUT_ZLP.v from AN65974, I only use the streamOUT mode

• Phenomenon : when I transfer data from host to fpga , I met the following situation.

1. Case1 : when I transfer data from host to fpga at first time, the FlagD can work,but the FPGA timing is not correct, as the picture 1.1 showed. When I transfer data from host to fpga at second time, the FlagD can’t work. When I transfer data from host to fpga at third time, the FlagD can’t work and the control center tell me “error 997”,as the picture 1.2 showed.
2. Case 2: after power off and restart the project, when I transfer data from host to fpga at first time, the FlagD can work,but the FPGA timing is not correct, as the picture 2.1 showed. However, the timing in picture2.1 is different from the timing in picture 1.1. When I transfer data from host to fpga at second time, the FlagD can work and I can get the correct data from fpga , as the picture 2.2 and picture 2.3 showed.

• Question:

1.      Can you help me to explain the different case? I never change any configurations for the project between case1 and case2.
2.     How can I transfer the data correctly?

AN79938 contains the recommended PAD design for NSMD. This document seems to have only information on 165-FBGA.

Is there any information on the recommended PAD design for the 121-BGA NSMD?

Thanks,

Tetsuo

There was an application in my project.Fpga transferred an ACK frame to the host when fpga received a CMD frame from the host.The length of ACK and CMD  is 32B.The GPIF II interface is a half_duplex interface, so how many CLKs should be kept at least bewteen writing and reading?I found that if set different CLKs between  reading and writing,it  would  go wrong.FPGA could recevie CMD frame correctly;I can capture the  time sequence of  writing,it is right;But  the  ACK frame received by xferdata funtion lost the first 4B,and the last 4B is 00000000;If i transferred CMD and recevied ACK by control center,it shows that the fx3 buffer only have 31B data.Could you give me some advice?thanks a lot.

Some based settings in my design:

datawidth:32bit

fclk:100MHz

watervalue: 6

buffer size :16KB

buffer count:2

Hi，i use the fx3 to set a data link between PC and FPGA. On the USB control center，0x01 0x03 0x81 0x83 bulk endpoint serve as data transmission in auto dma mode from GPIF-II to usb（fig-1），endpoint 0 work as command transmission channel。I use function CyU3PUsbSendEP0Data(dataLen,ep0Buf) （fig-2）to send back data ,use the controlendpoint class implementation Read(PUCHAR buf, LONG &len) (fig-3)on PC ,fx3 shows that fx3 ep0 has send the data successfully, but PC get a failure as shown fig-5. Has any invalid operation?HELP me,thx!

fig-1 (USB CONTROL CENTER )

fig-2(FX3 SDK EP0 send data code)

fig-3 (PC reading  ep0 data code)

fig-4 (fx3 uart print the statue of fx3 ep0 sending)

fig-5 ( print the status of PC ep0 data reading)

Following the threads here: Re: FX3 SDK version 1.3.4 won't put breakpoints while running  , is there a fix or workaround for this problem? The workaround suggested in the mentioned thread says to revert back to SDK 1.3.3. But as the OP in that thread pointed out, https://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-sdk-archives does not contain the Eclipse version and plugins that was included with SDK 1.3.3. Abhinav's reply in that thread says he attached the 1.3.3 SDK installer, but I don't see it. Can someone reupload the 1.3.3 SDK installer?

Thank you,

David

Hello there,

I am using a CYUSB3014 as a synchronous slave fifo interface to an Altera FPGA master.

I have modified the 2-bit slave fifo sync firmware (attached) by adding two endpoints and I'm using it to transfer data at an expected rate of about 80 MB/s. The FX3 should handle this without breaking a sweat, but instead I am getting a lot of dropped data.

I am probing the related DMA_Ready flag with Signal Tap in Quartus. I see that it goes low at some point during the transfer and stays so that for such a long time that I can't even seethe end of it within the Signal Tap time range. I have implemented a fifo in the FPGA as a buffer, but it's not enough.

Any help towards solving this issue would be really appreciated. Thanks in advance.

Dears.

I'm looking for the evaluation board with CYUSB3025-BZXI .

Could you give me your information ? Any information is OK for me even it's thirdparty solution circuit board.

Regards,

Kevin Han.

Hello

In my Application I need a Master GPIF to an FPGA with a 16-bit address bus. I want to transmit and receive data through the USB directly to the FPGA.

First question:

My plan is to send a control package to setup bulk transfers between the U-Port and the P-Port. With every setup package I would like to chose a new starting address, the number of data words and if the address counter will be incremented or not.

The only functions I found that give me control about the address counter and data counter are CyU3PGpifInitAddrCounter() and CyU3PGpifInitDataCounter(). I found somewhere here on the forum that these functions can be used only after loading the GPIF state machine but before starting it. Is that the correct way to implement a variable address and data counter? If yes, is it enough to disable the state machine with CyU3PGpifDisable(0) before reinitializing the address and data counter and then restarting it using CyU3PGpifSMStart()? Or is there a more direct way to access the address and data counter while the state machine is running?

Second question:

I want to have another option to send very short commands to the FPGA. For those I don't want to have an extra control package. But I want to send one package with my own header information I extract within the CPU. I use CyU3PGpifWriteDataWords() and CyU3PGpifReadDataWords() to write and read from the bus and the macro CY_U3P_PIB_GPIF_EGRESS_ADDRESS() to setup the address bus.

Writes are working fine when I use "OUT_REG0_VALID" as my transition equation. For reads I trigger the state machine through the FW_TRG transition by calling the commands CyU3PGpifControlSWInput(CyTrue) and CyU3PGpifControlSWInput(CyFalse). Now there is a relatively long delay between FW_TRG going low again. I need to add a state and the end of my read cycles that wait for !FW_TRG before going back to the IDLE state. Is this how it is supposed to be, when I intend to go through the CPU or is there another way to have quicker trigger mechanism.

Thanks

Background: I'm designing an interface where I paired an FPGA with the FX3. I opted to use the "Synchronous Slave FIFO Interface" to interface with the FPGA. The FPGA is paired with 512MB buffer memory. The FPGA should only send streaming (bulk) to the host PC (using USB3/FX3).

The "Synchronous Slave FIFO Interface" has 2 bit addressing mode by default. But I have 2 questions about this:

1) Is there a drawback/advantage in not using any addressing at all? It seems to me it would make the design simpler.

2) Can I change existing the GPIF-II design (sync_slave_fifo_2bit) and remove the addressbus? I see no way to do this, since there are only a few options under "Interface Customizations" in de GPIF-II Designer which don't include any settings for the addressbus, like when starting from scratch. If I start from scratch I see no way of copying the statemachine from the  Slave FIFO Synchronous", so that also seems rather cumbersome.

Any advice is highly appreciated.