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USB Superspeed Peripherals

KIMI_4749046
New Contributor II

I use CYUSB3KIT-003 KIT

I want to connect CYUSB3KIT-003 and Ultrascale FPGA Board.

I set up GPIF Master and want to use some signal and PCLK.

I know CYUSB3KIT support 1.8v and 3.3v voltage levels. I want to use 1.8v signal level.

But  J2 jumper is opend. the PCLK level is still 3.3v.

How can I use the pclk level is 1.8v. Please give me the idea.

Thanks.

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1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello,

We modified the GPIF master firmware (AN87216).

>> Please share the modified GPIF master firmware (used for your application) so that we can try to reproduce the issue at our end

When transferring bulk data, the peak voltage of CTL signals are over 1.8v.

>> Please measure the voltage at VIO while transferring data and share the result

1) How can I get the 1.8v on PCLK?

>> 1.8 V is expected at PCLK with the J2 jumper removed. As mentioned earlier, we measured the 1.8 V at PCLK with the default GPIF master firmware

>> Please try measuring the PLCK (with J2 removed) after programming the FX3 with default firmware attached with the application note AN87216 https://www.cypress.com/documentation/application-notes/an87216-designing-gpif-ii-master-interface

2) In Superspeed Explorer Kit, page 4 CVDDQ is V3P3.

Is it related with PCLK 3.3V?

>> No, the PCLK pin doesn't fall under the CVDDQ  power domain. Please refer to Table 7 of the  FX3 datasheet for pins falling under the CVDDQ power domain.

Regards,

Rashi

Regards,
Rashi

View solution in original post

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16 Replies
Rashi_Vatsa
Moderator
Moderator

Hello,

PCLK pin (GPIO [16]) falls under VIO1  power domain.

In CYUSB3KIT -003, Jumper J2 sets the voltage levels of the FX3 power domains VIO1, VIO2, and VIO3. Inserting the jumper selects 3.3 V while removing the jumper selects 1.8 V.

Please try resetting the device after removing J2 and then check the voltage level at PCLK

Regards,

Rashi

Regards,
Rashi
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KIMI_4749046
New Contributor II

After removing the jumper 2, I rechecked the voltage level at PCLK. The result is 3.3V.

At CYUSB3KIT 03, how can I use the voltage level 1.8 at P-PORT signals. and pclk.

I want GPIF Master IF as 1.8 voltage level.

The voltage level of the GPIO45, is 1.8v but VIO1 domain signals (DQ0~DQ15, PCLK, CTL0~12) are still 1.8 voltage level.

CYUSB301x spec describes CVDDQ.

CVDDQ is the supply voltage for clock and reset I/O. It should be either 1.8 V or 3.3 V based on the voltage level of the CLKIN signal.

But the schematic of SuperSpeed Explorer Kit has no CLKIN and CLKIN_32 pin source.

Instead it uses XTALIN and XTALOUT.

the schematic of SuperSpeed Explorer Kit has 3.3v voltage level of CVDDQ.

Is it related with PCLK voltage level 3.3v ?

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Rashi_Vatsa
Moderator
Moderator

Hello,

We have tried to reproduce the issue at out end.

1) Removed  the J2 jumper on CYUSB3KIT-003 (SuperSpeed explorer kit)

2) Programmed the FX3 with GPIF master firmware (AN87216)

3) Then measured the voltage level on PCLK and CTL pins. We are getting 1.8 V on PCLK and CTL (VIO1) pins.

- Please let me know if any changes were done to the CYUSB3KIT-003 board

- Please check the voltage on the VIO pin of the CYUSB3KIT-003 (after removing J2)

- Also, is it possible to check this with another CYUSB3KIT -003 kit

Regards,

Rashi

Regards,
Rashi
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KIMI_4749046
New Contributor II

I  have four CYUSB3KIT-003 boards and I have test them many times.

I got 3.3 V on PCLK and 1.8V on VIO.

I just removed JP2.

We modified the GPIF master firmware (AN87216).

Initially, CTL signals and VIO are 1.8V but PCLK is 3.3V.

When transferring bulk data, the peak voltage of CTL signals are over 1.8v.

I have some questions.

1) How can I get the 1.8v on PCLK ?

FPGA (1.8v) can not get the sync code through the GPIF master IF.

2) In Superspeed Explorer Kit, page 4 CVDDQ is V3P3.

Is it related with PCLK 3.3V?

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Rashi_Vatsa
Moderator
Moderator

Hello,

We modified the GPIF master firmware (AN87216).

>> Please share the modified GPIF master firmware (used for your application) so that we can try to reproduce the issue at our end

When transferring bulk data, the peak voltage of CTL signals are over 1.8v.

>> Please measure the voltage at VIO while transferring data and share the result

1) How can I get the 1.8v on PCLK?

>> 1.8 V is expected at PCLK with the J2 jumper removed. As mentioned earlier, we measured the 1.8 V at PCLK with the default GPIF master firmware

>> Please try measuring the PLCK (with J2 removed) after programming the FX3 with default firmware attached with the application note AN87216 https://www.cypress.com/documentation/application-notes/an87216-designing-gpif-ii-master-interface

2) In Superspeed Explorer Kit, page 4 CVDDQ is V3P3.

Is it related with PCLK 3.3V?

>> No, the PCLK pin doesn't fall under the CVDDQ  power domain. Please refer to Table 7 of the  FX3 datasheet for pins falling under the CVDDQ power domain.

Regards,

Rashi

Regards,
Rashi

View solution in original post

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KIMI_4749046
New Contributor II

Hello.

Thank you for your helping..

In my company, I cannot attach my source file.

Please give me your email address. I can send you source codes via Secure Trans.

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Rashi_Vatsa
Moderator
Moderator

Hello,

Thank you for the firmware.

1) In the firmware, the PCLK is 25 MHz Master mode please refer to this KBA Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733 which mentions the DLL settings for PCLK < 80MHz. Please set the DLL values as per Table 2 of the article and let me know if it helps.

2) Please let me know the voltage on PCLK when the default (not modified) GPIF Master firmware is programmed to FX3 (with J2 removed) meanwhile we will try to reproduce the issue at our end.

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello,

The DLL parameter settings that you have shared seems fine.

For the clock shifting problem, as mentioned in the KBA  Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733 , Wait for DLL Lock is "NO"

Please try commenting out this part of the CyFxApplnSetPibDllParameters API

/* Wait for DLL to lock */

    while (!(CY_FX3_PIB_DLL_CTRL_REG & CY_FX3_PIB_DLL_LOCK_STAT));

Please let me know the results after this modification.

For the PCLK voltage level issue, If possible, please try to probe PCLK with another scope and also confirm if the ground reference provided is proper. You can try connecting the ground pin of CRO to different ground pin on the board and check if there is some improvement in the voltage level.

Regards,

Rashi

Regards,
Rashi
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KIMI_4749046
New Contributor II

Using you recomended setting. I can get the GPIF low freq.

I changed "CY_FX3_PIB_DLL_OP_PHASE_POS" and got the clk phase shift.

    CY_FX3_PIB_DLL_CTRL_REG = (

            ((0xf & 0x0F) << CY_FX3_PIB_DLL_CORE_PHASE_POS) |

            ((0xf & 0x0F) << CY_FX3_PIB_DLL_SYNC_PHASE_POS) |

          // ((opPhase & 0x0F)   << CY_FX3_PIB_DLL_OP_PHASE_POS) |

            ((0x0 & 0x0F)   << CY_FX3_PIB_DLL_OP_PHASE_POS) |

            (0x1 << 16)|    // DLL_MODE -> SLAVE

            (0x46 << 17)|    // SLAVE_DELAY

            (0x0 << 1) | // CY_FX3_PIB_DLL_HIGH_FREQ |

            (0x7 << 27)|    // SLAVE_MODE

            (0x0 << 1) | // CY_FX3_PIB_DLL_HIGH_FREQ |

            CY_FX3_PIB_DLL_ENABLE

            );

But , voltage issue.

I changed my SCOPE Channel. but the voltage is still a little higher than 1.8v.

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Rashi_Vatsa
Moderator
Moderator

Hello,

1) Please let me know, is the slave is connected to FX3 when PCLK is being probed? If yes,  is it possible to probe the PCLK without connecting FX3 to the slave just to confirm that issue (high voltage than expected) is not due to the slave.

2) Also, let me know if you are you getting the clock frequency as expected?

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello,

Thank you for confirming that the PCLK frequency is as expected.

For the PCLK voltage issue, please try this for testing purpose

- Program another CYUSB3KIT-003 (not connected to slave/FPGA) with the GPIF master firmware.

- Then probe the PCLK (with and without J2 jumper) and share the results

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello,

From the hardware setup, that you have shared, we found that Jumper J5 is inserted even when SRAM is not used.

J5 must be inserted for applications that use the SRAM. It is recommended that you deselect the SRAM by removing J5 when the SRAM is not used. Note that the SRAM operates at 3.3 V and does not support 1.8-V signaling. Therefore, the SRAM must be deselected if the 1.8-V interface is selected (if J2 is removed, then J5 should also be removed)

Please remove J5 and J2 and then probe the PCLK without connecting the slave/FPGA

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello,

Please try the test on another CYUSB3KIT-003 which is not connected to the slave/FPGA

Test: remove J5 and J2 and then probe the PCLK after programming the FX3 with GPIF master firmware.

Regards,

Rashi

Regards,
Rashi
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Rashi_Vatsa
Moderator
Moderator

Hello,

In your previous reply, you mentioned that the clock is fine but the voltage is not as expected.  Please let me know with the DLL settings mentioned in the KBA were the clock edges proper previously?

Can you try testing the same firmware (with the new DLL settings as per the KBA) on standalone CYUSB3KIT-003 i.e. without connecting to the FPGA (removing J2 and J5 jumper) and let me know if you still see the same problem

Regards,

Rashi

Regards,
Rashi
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KIMI_4749046
New Contributor II

Thank for your help.

We succeeded to configure XCVU440 FPGA.

I designed the fx3 board schematic.

Is there anybody to check my schematic?

My company uses SECUARE TRANS FILE.

Please give me proper engineer's email.

Thanks

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KIMI_4749046
New Contributor II

I sended my schematic. Please review it.

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