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USB Superspeed Peripherals

user_1841156
New Contributor II

Hai,

     I am developing a USB 3.0 card with Cypress device(CYUSB3014)  and interface the external device with Xilinx Spartan 6(XC6SLX9-3TQG144C) device...i am using Control center Utility,to load the SFloopback.img file in ram,and under the configuration tree through Bulk out endpoint i send the data(Test.txt-5A 5A 5A 5A...) from usb host to Fx3. Program the xilinx with AN65974 vhdl file.so i click the Bulk in endpoint(Transfer data in) option,i didn't get loopback data,but some data comes incorrectly,and it was incremented contiously....

     My question is

1. Where the Bulk out Endpoint Data to be stored in Fx3 Device???

2.In AN65974 slave fifo xilinx file having fifo option,so why the loopback funcion not working properly???

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1 Solution
SrinathS_16
Moderator
Moderator

Hello,

- Please check if you have set the switch SW8 as per the table 6 in AN65974. For loopback applications, the SW8[4:1] must be set as

SW8[4:1] = OFF | ON | OFF | ON.

- In case you still face the failure, please probe the FX3-FPGA interface lines and share the captured waveform.

- The data sent from the BULK OUT endpoint is sent to the FPGA and is not stored in FX3 device. (FX3 only provides a temporary storage of data in its internal FIFO buffers). The FPGA then loops back the data to the FX3, which sends it to the host over the BULK IN endpoint.

Best regards,

Srinath S

View solution in original post

11 Replies
SrinathS_16
Moderator
Moderator

Hello,

- Please check if you have set the switch SW8 as per the table 6 in AN65974. For loopback applications, the SW8[4:1] must be set as

SW8[4:1] = OFF | ON | OFF | ON.

- In case you still face the failure, please probe the FX3-FPGA interface lines and share the captured waveform.

- The data sent from the BULK OUT endpoint is sent to the FPGA and is not stored in FX3 device. (FX3 only provides a temporary storage of data in its internal FIFO buffers). The FPGA then loops back the data to the FX3, which sends it to the host over the BULK IN endpoint.

Best regards,

Srinath S

View solution in original post

user_1841156
New Contributor II

Hai Srinath,

    I am not using Xilinx Sp601 Development Kit to interface with Fx3. I am using my own development Board

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SrinathS_16
Moderator
Moderator

Hello,

The FPGA project that comes with the AN65974 makes use of the GPIOs for monitoring the SW8 connected on SP601 board. FPGA decides the nature of data stream based on this switch setting. Hence, it is essential that you modify your FPGA code to implement the same behavior on your board. Please let me know if you have implemented this modification.

Best regards,

Srinath S

user_1841156
New Contributor II

Hai,

    You are saying,the data sent from the BULK OUT endpoint is sent to the FPGA and is not stored in FX3 device. (FX3 only provides a temporary storage of data in its internal FIFO buffers). The FPGA then loops back the data to the FX3, which sends it to the host over the BULK IN endpoint.

   Ok then what the use of GPIO's DQ(31:0)???

If i send the data through host (Eg:5A 5A 5A 5A), then i getting DQ(31:0) is to be 0.

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SrinathS_16
Moderator
Moderator

Hello,

The DQ[31:0] pins form the path for data transfer over the GPIF II interface. When you are trying to send data 5A 5A ... over the GPIF II interface, the DQ[31:0] pins will be alternatively 0 and 1.

Please share the FX3 firmware source that you are using in case you have made any modifications to the AN65974 firmware.

Best regards,

Srinath S

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user_1841156
New Contributor II

Hai Srinath,

    Actually i send the 5A 5A 5A 5A...(Test.txt file)  through Bulk OUT Endpoint using SF_loopback.img.  I am using FPGA as a master and FX3 as a slave. In the loopback function mode,the FPGA reads the data which i send to FX3 Buffer(Through Control Center->Bulk OUT Endpoint) and Writes back to the FX3 Buffer (Through Control Center->Bulk IN Endpoint)) because it has dual port.

  Same like that i send the data through Bulk out Endpoint(5A 5A 5A 5A..),but when i click the Bulk in Endpoint,the same data didn't loopback.The result is incremented continously and i probed the data lines through scope I am getting some results.

      Herewith i attached the photos for your reference...i attached the output of data lines images ( named as DQ0,1,2,3,4,5 OUTPUT ) and control center result images (named as Bulk in endpoint 1,2,3,4,5)

The output of data lines is DQ0 having 64 patterns,DQ1 having 32 patterns,DQ2 having 16 patterns,DQ3 having 8 patterns,DQ4 having 4 patterns,DQ5 having 2 patterns,DQ6 having 1 pattern etc...

Why the result coming below like that?.Any idea please share with me...

Bulk in endpoint output_1st click.jpgBulk in endpoint output_2nd click.jpgBulk in endpoint output_3rd click.jpgDQ0_output.JPGDQ1_output.JPGDQ2_output.JPGDQ3_output.JPGDQ4_output.JPGDQ5_output.JPG

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user_1841156
New Contributor II

Hai Srinath,

In the Scope Images,the yellow colour is SLWR and Red colour is Data line DQ.

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SrinathS_16
Moderator
Moderator

Hello,

Please check if the data received on the USB Control Center correspond to the data on the DQ[31:0] lines. If yes, then the FX3 firmware is working fine and the FPGA code needs to be checked. If the data doesn't match, then the FX3 has got issues. Please test this and let us know the results. In case you have modified the FPGA code to suit your FPGA device, make sure that the loopback implementation is carried out properly.

Best regards,

Srinath S

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user_1841156
New Contributor II

Hai Srinath,

    I am Using Slavefifosync 2bit program for Communication.The example application C program writes for using UART configuration.But my design,i am using DQ32 Bits.So how can i modify the program from UART To DQ32BITS.

Thanks & Regards,

Shenbagaraj Arun.P

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user_1841156
New Contributor II

Hai,

    Can you change and send the cyfxslfifosync.c program from UART to DQ32BITS.

Regards,

Shenbagaraj Arun.P

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SrinathS_16
Moderator
Moderator

Hello Shenbagaraj Arun,

The firmware that comes with the AN65974 implements both 16-bit as well as 32-bit GPIF II interface. The UART is enabled in both the configurations to implement debug logging.

Best regards,

Srinath S

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