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USB Superspeed Peripherals

SeCe_4603466
New Contributor II

Hello,
I am opening this discussion on behalf of a colleague who can't speak English and I am not familiar with the subject here.

I hope it gets across fine enough and I appreciate any help on this.

He wants to do either of two thing below. His preference is for the second one but he feels he can't hope for it. Either one works in the end.

Please see attachments for his references.

1)

When FIFO0 is full, I want to switch from FIFO0 to FIFO1 as shown below. Is it possible to do this within 80nS (red in below diagram)?

In the manual it says that it takes several μSs, but i am not sure if I understand it right?

2)

Is it possible to send data of FIFO0 immediately when it is FULL and within 80 nSs make it ready to write next data?

Thank you very much and best regards

Sevgi

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

Thank you for providing the details accurately. I found from your first attachment that the data bus width for GPIF II block is 32 bits. I understood that you are using 2 current thread flags (one ready flag and other a partial flag).

The general formula for using partial flag for write operation is mentioned in section 9.3 of AN65974. For write operation, this is

Number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark * (32/bus width) - 4.

I  also understood that the interface frequency is 100MHz. So one clock cycle is 10ns.

The second option which you asked at the beginning is not possible. The first option can be achieved. This can be done in the following way. Consider a write operation to the slave FIFO. Configure the watermark value for the partial flag as 4. So that the number of data words that may be written after the clock edge at which the partial flag is sampled low will be 0 (from section 9.3 of AN65974).  At the start of the write operation, the master will assert the address lines A1:A0. After the assertion of address lines, at the third clock edge(starting from the clock edge where address lines were asserted), the status of the flag will be valid. Make sure that at the start of the transfer you sample ready flag itself. This is because partial flag shows a different behaviour at the start of transfer.

Now when the last data word to be written is reached, the partial flag will go low. After sampling the partial flag low, the master should de-assert the write signal and switch the thread by changing A1:A0. At the third clock edge after sampling the address lines, the ready flag corresponding to the new thread becomes valid. If the flag shows ready condition, then next write can start.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

4 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Please provide answers for my following questions:

1.What do you refer to by "FIFO", is it a GPIF thread or a DMA Buffer?

2.What is the interface clock which you are planning to use?

3.When one FIFO is full, how can the master know about it? Is this done by using FLAGs from the P Port of FX3 or do you have any other implementations on FPGA to track this?

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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SeCe_4603466
New Contributor II

Hello Jayakrishna,

Thank you for your answer.

1. It is GPIF. Planning to move it with Synchronous Slave FIFO Interface (marked red on page 4 of attached manual)

2.It is 100MHz. (marked red on page 10 of attachment)

3. I am planning to use the FLAGs marked red on page 14 of attached manual.

But i can do it on FPGA as well.

Best regards,

Sevgi

JayakrishnaT_76
Moderator
Moderator

Hello,

Thank you for providing the details accurately. I found from your first attachment that the data bus width for GPIF II block is 32 bits. I understood that you are using 2 current thread flags (one ready flag and other a partial flag).

The general formula for using partial flag for write operation is mentioned in section 9.3 of AN65974. For write operation, this is

Number of data words that may be written after the clock edge at which the partial flag is sampled low = watermark * (32/bus width) - 4.

I  also understood that the interface frequency is 100MHz. So one clock cycle is 10ns.

The second option which you asked at the beginning is not possible. The first option can be achieved. This can be done in the following way. Consider a write operation to the slave FIFO. Configure the watermark value for the partial flag as 4. So that the number of data words that may be written after the clock edge at which the partial flag is sampled low will be 0 (from section 9.3 of AN65974).  At the start of the write operation, the master will assert the address lines A1:A0. After the assertion of address lines, at the third clock edge(starting from the clock edge where address lines were asserted), the status of the flag will be valid. Make sure that at the start of the transfer you sample ready flag itself. This is because partial flag shows a different behaviour at the start of transfer.

Now when the last data word to be written is reached, the partial flag will go low. After sampling the partial flag low, the master should de-assert the write signal and switch the thread by changing A1:A0. At the third clock edge after sampling the address lines, the ready flag corresponding to the new thread becomes valid. If the flag shows ready condition, then next write can start.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

SeCe_4603466
New Contributor II

Hello Jayakrishna,

This was very helpful, thanks a lot.

My collegue is working on it now.

Best regards,

Sevgi

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