USB low-full-high speed peripherals Forum Discussions

Hi. All.

This question is related with AN61345 application. link https://www.cypress.com/documentation/application-notes/an61345-designing-ez-usb-fx2lp-slave-fifo-interface

My customer asked why is different between slave.iic file(in zip folder *) and slave.iic after keil compile.

* AN61345 Designing With EZ-USB FX2LP Slave FIFO Interface - Source code.zip

They said the original file is ok on their board but the compiled file is some strange.

We changed product ID to 0310. then, We found the descriptor is changed to FX2LP. but the working is not same.

It is not same the hex file and iic file  after compile.

Could you explain what is a problem? and Can you share Previous AN61345 FW if you have?

Regards.

Robert.

I have below error during building project.

Error: Program "make" not found in PATH

Thanks

Esakki

Hello everyone,

I am beginner working with CYUSBS234, I tried testing SPI communication with internal EEPROM and I had successful results, but now I want to use SPI communication to write data in a flash memory (chip 6D25Q64C), I connected #2 pins of J17, J19, J20, and J21 to the external chip according with https://community.cypress.com/docs/DOC-10837​ but now I dont know how to procedure, I tried using the USBSerialTest Utility, I clicked the "Write data" button, but when I clicked the "Read & verify data" button, a warning message tell me that the data verification failed, and shows me the buffer data which always is full of zeros.

Could anyone of you help me please?

Can the CYUSBS234 DVK have the CY7C65211 swapped out with the A version to be configured in SPI mode as a virtual COM port? If so will the configuration utility allow the SPI configuration?

Can I use a development kit CY3684 to debug the firmware for CY7C68014A-56PVXC?  The development kit uses the CY7C68013A-128AXC which also has access to the serial port  for the KEIL debugger.  I don't need all the functionality of the 128 pin part and the power consumption is also a benefit is the reason to use CY7C68014A-56PVXC

Thanks in Advance!

Chris

Hi Sir,

客户的产品是各种摄像头模组，通过CY7c68013将图像数据传递给手机，客户的产品已经量产，最近客户反馈，在华为的新款的手机无法识别CY7c68013，并且只在华为的新款手机上无法识别，手机年份大概2018年以后的都不行,以下是客户提供的手机系统的截图，请问这是什么原因呢，谢谢。

Hi Sir,

Customer's product is all sorts of camera module, through CY7c68013 pass image data to mobile phone, the customer's products have been mass production, customer feedback recently, in huawei's new phone unable to identify CY7c68013, and only in huawei's new mobile phone can't identify, mobile phone probably after 2018 year are not, the following is screenshot provide mobile phone system, what reason is this excuse me? Thank you.

YatheeshK_36​RajathB_01​

Hi , this s sabitha here , am working on cypress usb to dual uart ic ( cy7c65215a) , I configured this ic in self powered morde i.e vbus supply 3.3v given seperately and vccio is also given 3.3v . now the problem is usb not detected i dono why?????, In usb connector first pin deccoupled through 0.1uf, Please give me the suggestion

Hi, how to use this pin?

I do not let the 8051 core into power down mode forever?

How could I set this pin?

connect to  vcc or ground,  directly?

Thanks.

Good afternoon Cypress. I worked with the cy7c67300 eeprom on the xilinx ml605 board, I figured it out for a long time and finally was able to flash it with qtui2c, but it stopped displaying in the computer. You can send me the factory EEPROM, and / or the source code for it.

The FAQs mention that it is acceptable to apply VCCIO before VCC for CY7C65213:

USB-Serial Bridge Controller FAQs - KBA224054

Does this imply that for CY7C65211 it is ok to apply VCCIO before VBUS?

We are considering to use the CY7C65211 in a battery-powered design with 1.8 V IO levels.

We can only supply VBUS from the actual USB port (no other 3.3V or 5V source available),

but could sequence VCCIO with respect to VBUS at best in software (so VCCIO starts a few ms after VBUS)

or simply keep it on at all times (VCCIO is present when VBUS is not).

Is either of those configurations acceptable as long as we ensure XRES is kept low until both rails are stable?