About the phase for FX2LP

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Hello

Regaring the CY7C68013A-56PVXC.pdf Japanese version (document number: 001 - 63322 Rev. D).

They are checking both Figure 18 on page 46 and Figure 20 on page 48.IFCLK in the figure should be supplied internally.

The clock to be supplied seems to be able to select the phase with the program of FX2 (below)

● Clock phase selection (Phase can be selected when selecting internal supply)

1) Make the phase of IFCLK in phase with IFCLKi inside FX2.

2) Make the phase of IFCLK inverse to IFCLKi inside FX2.

Q)

They are programming it with reverse phase of 2) mentioned above.In this case, what about the standards in Figures. 18 and 20?

They are undrstanding that Figures 18 and 20 as charts of the same phase (above selection 1) ).

Is there a chart or standard when IFCLK is in reverse phase?

Best Regards

Arai

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.
Sananya_14
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello Arai-san,

When the phase of the clock is inverted as Case 2, and the clock source is internal, the phase is changed on the IFCLK output (if enabled) and not for IFCLK used in the slave FIFO interface. This helps meet the timing requirements of the FLAGS signals on the master side as explained in the attached figure. The setup and hold time requirements for SLRD and the turn on and turn off time for SLOE must be set according to Table 22 (for Figure 20) itself since the internal IFCLK without the phase change will be used for data transfers.

Best Regards,

Sananya

View solution in original post

0 Likes
4 Replies
lock attach
Attachments are accessible only for community members.
Sananya_14
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello Arai-san,

When the phase of the clock is inverted as Case 2, and the clock source is internal, the phase is changed on the IFCLK output (if enabled) and not for IFCLK used in the slave FIFO interface. This helps meet the timing requirements of the FLAGS signals on the master side as explained in the attached figure. The setup and hold time requirements for SLRD and the turn on and turn off time for SLOE must be set according to Table 22 (for Figure 20) itself since the internal IFCLK without the phase change will be used for data transfers.

Best Regards,

Sananya

0 Likes
NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Hello Sananya san

Just in Case, i want to check below.

Q1)When the phase of the clock is inverted as Case 2), and the clock source is internal, the figure(timing diagram) is not described in data sheet. Because figure 18 and 20 are described as case 1).

Is it correct asuuming?

Q2) If there is no figure for CASE 2), is there a document for standard?

Best Regards

Arai

0 Likes

Hello Arai-san,

The assumption seems to be incorrect as per my understanding since the clock phase will be inverted only on the output from IFCLK and the timing specifications in Figure 18 and 20 will still be valid. On the FX2LP slave FIFO interface, there is no inversion on the internal IFCLK input which is used for clocking the DATA, SLRD, SLOE signals and requires the setup timings as per the Tables in the datasheet. Please refer to section 9.2.3 in the Technical reference manual for more details if the above explanation seems confusing.

Best Regards,

Sananya

0 Likes
NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

I understood. Thank you for your reply

Best Regards

Arai

0 Likes