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I have 68013A chip configured as slave fifo. After i download a firmware I see that enumeration occurs. Than I'm trying to perform the asynchronous write. I select the EP6 endpoint and i see that FLAFB and FLAGC are both high (+3.3V). As FLAG pins are configured as active low that means that EP6 edpoint is not empty and not full.
What that supposed to mean? I didn't performed any write operations to that endpoint.
Thanks.
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Hi,
Please upload TD_Init portion of your file.
Thanks,
Prajith
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Hi Prajith,
Thanks for reply.
I solved the problem with flags. The reason was that i was writing some data to FIFO so fifo was not full and not emty. No flags seems to be working fine.
I found another strange thing with FLAGS.
I'm currently using EzMr.exe program to load firmware to the chip and to write some data to OUT fifos.
I have EP2 endpoint configured as OUT. From masters side i select FIFO EP2 and I see that FLAGC is zero. It means that EP2 is empty. Ok. When i'm performing BULK transfer to EP2 from EzMr.exe the FLAGC goes to 1 meaning that EP2 is not empty.
I found that when i'm writing to EP4 which is also OUT endpoint. The FLAGC also goes to 1 though i have selected EP2 via FIFOADR. That's strange.
Here is my TD_Init() part.
void TD_Init(void) // Called once at startup
{
BYTE tmp;
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
// set the slave FIFO interface to 48MHz
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
tmp = USBIRQ;
if( 1 )
{
IFCONFIG = ( bmIFCFG1 + bmIFCFG0 + bmASYNC + bmIFCLKSRC + bm3048MHZ);// Async mode
// endpoint 2
SYNCDELAY;REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY;EP2CFG = 0xA2;
SYNCDELAY;EP4CFG = 0xA2;
//SYNCDELAY;EP4CFG = 0x22; //disable ep4 (saniok)
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x02;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP2FIFOCFG = bmWORDWIDE; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=1, WORDWIDE=1
SYNCDELAY;OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY; EP2BCL = 0x00; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP2BCL = 0x00;
SYNCDELAY; EP2BCH = 0x02; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP2BCH = 0x02;
// abort pipe
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x04;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP4FIFOCFG = bmWORDWIDE; // EP4 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=1
SYNCDELAY;OUTPKTEND = 0x84; // Arm both EP4 buffers to “prime the pump”
SYNCDELAY;OUTPKTEND = 0x84; // Arm both EP4 buffers to “prime the pump”
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY; EP4BCL = 0x00; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP4BCL = 0x00;
SYNCDELAY; EP4BCH = 0x02; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP4BCH = 0x02;
SYNCDELAY;EP6CFG = 0xE2; // EP6 is DIR=IN, TYPE=BULK
//SYNCDELAY;EP6CFG = 0x62;//disable ep6 (saniok)
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x06;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP6FIFOCFG = bmAUTOIN + bmWORDWIDE; // EP6 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;EP6AUTOINLENH = 0x02; // Auto-commit 512-byte packets
SYNCDELAY;EP6AUTOINLENL = 0x00;
SYNCDELAY;EP8CFG = 0xE2; // EP8 is DIR=IN, TYPE=BULK
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x08;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP8FIFOCFG = bmAUTOIN + bmWORDWIDE+bmZEROLENIN; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;EP8AUTOINLENH = 0x02; // Auto-commit 512-byte packets
SYNCDELAY;EP8AUTOINLENL = 0x00;
FIFOPINPOLAR = 0x00;
}
else
{
IFCONFIG = ( bmIFCFG1 + bmIFCFG0 + bmASYNC+ bmIFCLKSRC + bm3048MHZ);// Async mode
SYNCDELAY;REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY;EP2CFG = 0xA2;
SYNCDELAY;EP4CFG = 0xA2;
//SYNCDELAY;EP4CFG = 0x22; //disable (saniok)
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x02;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP2FIFOCFG = bmWORDWIDE; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=1, WORDWIDE=1
SYNCDELAY;OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY; EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP2BCL = 0x80;
// abort pipe
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x04;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP4FIFOCFG = bmWORDWIDE; // EP4 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=1
SYNCDELAY;OUTPKTEND = 0x84; // Arm both EP4 buffers to “prime the pump”
SYNCDELAY;OUTPKTEND = 0x84; // Arm both EP4 buffers to “prime the pump”
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY; EP4BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; EP4BCL = 0x80;
SYNCDELAY;EP6CFG = 0xE2; // EP6 is DIR=IN, TYPE=BULK
//SYNCDELAY;EP6CFG = 0x62; // EP6 is DIR=IN, TYPE=BULK
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x06;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP6FIFOCFG = bmAUTOIN + bmWORDWIDE; // EP6 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;EP6AUTOINLENH = 0x00; // Auto-commit 64-byte packets
SYNCDELAY;EP6AUTOINLENL = 0x40;
SYNCDELAY;EP8CFG = 0xE2; // EP8 is DIR=IN, TYPE=BULK
SYNCDELAY;FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;FIFORESET = 0x08;
SYNCDELAY;FIFORESET = 0x00;
SYNCDELAY;EP8FIFOCFG = bmAUTOIN + bmWORDWIDE+bmZEROLENIN; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;EP8AUTOINLENH = 0x00; // Auto-commit 64-byte packets
SYNCDELAY;EP8AUTOINLENL = 0x40;
FIFOPINPOLAR = 0x00;
}
PORTACFG = 0x40; //FLAGD ALTERNATE (CLCS) SHARANDA
IOE = _int_dsp_;
OEE |= ( _int_dsp_ | _usb_20_);// output INT signal to DSP;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
Rwuen = TRUE; // Enable remote-wakeup
}
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Hi,
Your code worked as expected.I made two bulk transfers for each out endpoint(EP2OUT and EP4OUT)and got FlagC(Full)=0 and Flagb(Empty)=1. It is expected since we dont commit endpoints in your code. But I couldnt reproduce your observation.Do you commit packets in TD_Poll??. Anyway, let me check your project file also.
Thanks
Prajith