dpm_update_src_cap_mask vaule

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Flance_Fang
Level 4
Level 4
Distributor - Weikeng(GC)
50 sign-ins 50 questions asked 25 sign-ins

Hi. cypress

In newly update PDO, there has dpm_update_src_cap_mask (uint8_t port, uint8_t mask); in your example PDO[4], you sent the mask is 0F, my question how to calculate the value 0X0F, in the other example, it is 0X1F as below:

void change_pdos(void)

{

  pd_do_t SRC_PDO[4];

    if ( //read pin status register somewhat way == false)

    {

        SRC_PDO[0].val = 0x0001912C; //5V 3A (This value can check on xml file created by EZ-PD Configuration Utility)

        SRC_PDO[1].val = 0x0002D0D2; //9V 2.1A

        SRC_PDO[2].val = 0x0004B12C; //15V 3A

        SRC_PDO[3].val = 0x0006412C; //20V 3A

    

        dpm_update_src_cap(0, 4, SRC_PDO);

        dpm_update_src_cap_mask (0, 0x0F);

        dpm_pd_command (0, DPM_CMD_SRC_CAP_CHNG, NULL,NULL); //Send PD command about the changes in source capabilities

    }

}

CY_ISR(GPIO_ISR_handler)

{

    //clear any active interrupts on corresponds pin for interrupt

    change_pdos();

}

second example:

void change_pdos(void)

{

   pd_do_t SRC_PDO[5];

    SRC_PDO[0].val = 0x0B01912C;

    SRC_PDO[1].val = 0x0002D0C8;

    /* New 15V PDO to be added */

    SRC_PDO[2].val = 0x0004B064;

    SRC_PDO[3].val = 0xC0761E3C;

    SRC_PDO[4].val = 0xC0DC1E3C;

   

    /**

     * @brief This function updates the source PDOs at runtime thereby overriding

     * the source PDOs in the configuration table.

     * @param port Port index.

     * @param count Count of PDOs.

     * @param pdo Pointer to the PDO array.

     * @return CCG_STAT_SUCCESS if operation is successful, CCG_STAT_BAD_PARAM

     * otherwise.

     */

    dpm_update_src_cap(0, 5, SRC_PDO);

       

    /**

     * @brief This function updates the source PDO mask at runtime thereby

     * overriding the source PDO mask in the configuration table.

     * @param port Port index.

     * @param mask PDO mask.

     * @return CCG_STAT_SUCCESS if operation is successful, CCG_STAT_BAD_PARAM

     * otherwise.

     */

    dpm_update_src_cap_mask (0, 0x1F);

   

    dpm_pd_command (0, DPM_CMD_SRC_CAP_CHNG, NULL,NULL); //Send PD command about the changes in source capabilities 

}

/*

*   Interrupt Service Routine to handle the interrupts triggered

*   on the falling edge of the GPIO_0 input signal

*/

CY_ISR(GPIO_ISR_handler)

{  

    GPIO_0_ClearInterrupt();   // Clears any active interrupts attached with the GPIO_0 component   

   

    /* update the source PDOs */

    change_pdos();

}

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1 Solution
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi ,

I guess you want to understand the relates of SOURCE_CAP NUMBER and src_cap_mask.

For the 0x0F example, you have updated 4 source caps, so that the bit 0, 1, 2, 3 shall be enabled in src_cap_mask, so that the src_cap_mask = 0000 1111b = 0x0F.

For the 0x1F example, you have updated 5 source caps, so that the bit 0, 1, 2, 3, 5shall be enabled in src_cap_mask, so that the src_cap_mask = 0001 1111b = 0x1F.

The format of src_cap_mask is bit [7...0] = { N/A,Sourc_cap 6,  Sourc_cap 5,  Sourc_cap 4,  Sourc_cap 3,  Sourc_cap 2,  Sourc_cap 1,  Sourc_cap 0}.

Best Regards,

Lisa

View solution in original post

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1 Reply
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi ,

I guess you want to understand the relates of SOURCE_CAP NUMBER and src_cap_mask.

For the 0x0F example, you have updated 4 source caps, so that the bit 0, 1, 2, 3 shall be enabled in src_cap_mask, so that the src_cap_mask = 0000 1111b = 0x0F.

For the 0x1F example, you have updated 5 source caps, so that the bit 0, 1, 2, 3, 5shall be enabled in src_cap_mask, so that the src_cap_mask = 0001 1111b = 0x1F.

The format of src_cap_mask is bit [7...0] = { N/A,Sourc_cap 6,  Sourc_cap 5,  Sourc_cap 4,  Sourc_cap 3,  Sourc_cap 2,  Sourc_cap 1,  Sourc_cap 0}.

Best Regards,

Lisa

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