USB EZ-PD™ Type-C Forum Discussions

Hello

I'm thinking of creating a simple board that can program PMG1-S3 FW using "Miniprog４”. Just in case, please check if there is no problem with the attached schematic.

Best Regards

I instrumented the PDO code (see below) to display the SRC advertisements via the debug uart and monitored the bus with an analyzer.  The fixed PDO's decode properly, but the variable/pps PDO's make no sense.  The analyzer shows the external Source advertizing pps:3.30-21.00v.  The eval_src_cap(...) shows this as 13200 1300 3560.  Is this a library issue? 

for(src_pdo_index = 0u; src_pdo_index < srcCap->len; src_pdo_index++) {
if (srcCap->dat[src_pdo_index].fixed_src.supplyType == CY_PDSTACK_PDO_FIXED_SUPPLY){

...

 } else {   //if (srcCap->dat[src_pdo_index].fixed_src.supplyType == CY_PDSTACK_PDO_VARIABLE_SUPPLY) {

Trying to get familiar with the CY7113 EZ PD kit.

I can build the simple Hello Worls and run it with Teraterm getting expected results.

Trying to use the OCD debugger fails on both Helloe Worls and PD SINK apps with:  Error: BUG: refcount AP#0 still 2 at exit

Upgraded to Modus 3.1 and reprogrammed the debugger with latest FW but no improvement.  Any Ideas?

Started by GNU MCU Eclipse
Open On-Chip Debugger 0.12.0+dev-5.0.0.2401 (2023-05-16-04:28)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
** Auto-acquire enabled, use "set PSOC4_USE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf155, serial=1C090A8800121400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.50.1383
Info : KitProg3: Pipelined transfers enabled
Info : KitProg3: Asynchronous USB transfers enabled
Info : VTarget = 3.250 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x0bc11477
Info : [psoc4.cpu] Cortex-M0+ r0p1 processor detected
Info : [psoc4.cpu] target has 4 breakpoints, 2 watchpoints
*****************************************
** Silicon: 0x3501, Family: 0xC5, Rev.: 0x12 (A1)
** Detected Family: PMG1-S3
** Detected Device: CYPM1311-48LQXI
** Detected Main Flash size, kb: 256
** Chip Protection: OPEN
*****************************************
Info : gdb port disabled
Info : starting gdb server for psoc4.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : SWD DPIDR 0x0bc11477
Info : kitprog3: acquiring the device (mode: reset)...
[psoc4.cpu] halted due to debug-request, current mode: Thread
xPSR: 0xa1000000 pc: 0x10000040 msp: 0x20007fe8
** Device acquired successfully
Started by GNU MCU Eclipse
Error: couldn't bind tcl to socket on port 6666: No error
Error: BUG: refcount AP#0 still 2 at exit
Info : psoc4.dap: powering down debug domain...

Hello

If the CYPD3171 "CSP" pin is not used, what kind of unused pin processing is recommended?

Best Regards

1. what different Host - behavior between enabled vPRO and disabled vPRO capable?

2. What is Hybrid Boot Architecture?

Customer has new project using  AMD barcelo platform,

Which version of Host SDK  and project should we use for development - AMD barcelo?

We don't know about architecture for AMD barcelo platform, does PD have to communicate with AMD SOC?

Hello,

I am trying to do I2C communication with PMG1.

Does the I2C Cy_SCB_I2C_MasterSendStart function check the bus busy status before starting?

Regards.

SheetHello

Regarding the following description of 1.4 I/O subsystem on Page 6 of the CCG3PA Data-Sheet

The GPIO block implements the following:

>Seven drive strength modes:

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

（Q1）Could you tell us about the "Resistance value" for each of the above weak pull-up and strong pull-up?

Regarding the following description "3 Pinouts" on Page8 of the CCG3PA Data-Sheet.

>4. AXRES pin will be internally pulled up during the Power On I/O initialization >time (See Table 7 for more details)

(Q2) Above, the AXRES pin is described as an initial pull-up, but is it a weak pull-up or a strong pull-up?

Best Reards

Hi,

These pins drive the consumer path FET's. I measured gate voltage 10.5V with 5V VBUS supply. This seems to be good marginal to get low Rds for the FET's. However when PD negotiates 20V/3A VBUS (measured 19.7V) the gate voltage is mere 20.5V.  The FET heats up on higher currents so I assume reason is the low gate voltage and thus too high Rds.

What kind of  driver voltage I should expect to see on 20V VBUS, I assume it should be around 25V?
We're using CYPD3120.