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Hi,
we are working with CCG5 (CYPD5225-96BZXI) and SDK 3.3.0.
Our board is currently under certification tests and results that USB-C Function Test fail on:
TD 4.6.5 Try.SRC DRP Connect Sink Test
PD 2.0 5A Active Cable -> For a PUT_R, the PUT must provide Rp on both CCS.
PD 3.0 5A Active Cable -> The PUT connects the SS pairs after 80 ms.
Looking at https://www.usb.org/sites/default/files/USB_Type_C_Functional_Test_Specification_2018_05_28.pdf, we found that TD 4.6.5 test fails on steps D.2.c.i and D.6.a.i.
We haven't found any connection between CCG5 firmware configuration or external HW layout connected to CCG5 and actions involved in test procedure, but seems that all is managed by CCG5 firmware internal routine.
Did you receive any feedback about this issue?
Is there any aspects on firmware configuration or external HW layout connected to CCG5 to focus on?
Best regards.
Solved! Go to Solution.
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Hi Massimo,
As per the test report and firmware you attached, below is the comments for your reference.
PD 2.0 5A Active Cable -> For a PUT_R, the PUT must provide Rp on both CCS:
CCGx firmware always applied Rp on both CC lines. If this is failing, I would like to recommend you check whether the hardware is wrong (not connecting one of the CC lines). It seems there is only one CC connection on CCG5.
PD 3.0 5A Active Cable -> The PUT connects the SS pairs after 80 ms:
CCGx firmware have a compile time configuration called MUX_INIT_DELAY_MS which can be set in the project to define the time required for SS MUX to be enabled before VBus turns on. This should be set to an appropriate value based on your hardware to pass the test.
Best Regards,
Lisa
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Could you please share the firmware HEX file you were testing and VIF of your project in this threads?
Could you please confirm which firmware version you are using?
Best Regards,
Lisa
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Hi Massimo,
As per the test report and firmware you attached, below is the comments for your reference.
PD 2.0 5A Active Cable -> For a PUT_R, the PUT must provide Rp on both CCS:
CCGx firmware always applied Rp on both CC lines. If this is failing, I would like to recommend you check whether the hardware is wrong (not connecting one of the CC lines). It seems there is only one CC connection on CCG5.
PD 3.0 5A Active Cable -> The PUT connects the SS pairs after 80 ms:
CCGx firmware have a compile time configuration called MUX_INIT_DELAY_MS which can be set in the project to define the time required for SS MUX to be enabled before VBus turns on. This should be set to an appropriate value based on your hardware to pass the test.
Best Regards,
Lisa