How do I start if I want to modify OCP and OVP function of CCG4?

Announcements

Live Webinar: USB-C adoption. Simple & Cost-efficient solutions | April 18th @9am or 5pm CEST. Register now !

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable

Hi there,

We have modified the circuit of OVP and OCP from EVK of CCG4. How do I start to modify code happen? Should I modify source code directly or use EZ-PD utility first.

Actually, we have more customized circuit from CCG4 EVK.

Modification

1. The EC host boot loader function without the HCI pin. We wanna update from I2C directly.

2. The OVP and OCP has been use some GPIO as notified pin.

3. Sink or Source path control.

We would like to modify to as we want.

Where should we start? Go to source all the way or still need EZ-PD configuration ?

Jason

0 Likes
1 Solution
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi Jason,

1. If you are not going to support HPI, what's you are process shall be follow Cypress HPI via I2C. For example, you need clear INT with I2C command. And then enter flash mode to upgrade firmware.

2. For OCP, CCG4 (Refer CY4541 kits hardware schematic) VBus OCP feature is implemented based on an external load switch and only uses a fault indicator GPIO coming into the CCG device. The default setting is VBUS_OCP_MODE == VBUS_OCP_MODE_EXT.

Since you are changed OCP hardware, please kindly change pin assignments in .cydwr file and change the OCP mode as per your hardware.

The MODE SDK have been defined @file pdss_hal.h:

#define VBUS_OCP_MODE_EXT               (0u)  /**< OCP through external hardware. */

#define VBUS_OCP_MODE_INT               (1u)  /**< Internal OCP without software debounce or hardware gate control. */

#define VBUS_OCP_MODE_INT_AUTOCTRL      (2u)  /**< Internal OCP with hardware gate control. */

#define VBUS_OCP_MODE_INT_SW_DB         (3u)  /**< Internal OCP with software debounce. */

#define VBUS_OCP_MODE_POLLING           (4u)  /**< Solution level polling based OCP. */

#define VBUS_OCP_GPIO_ACTIVE_LOW        (0u)  /**< GPIO low indicates fault condition. */

#define VBUS_OCP_GPIO_ACTIVE_HIGH       (1u)  /**< GPIO high indicates fault condition. */

3. For OVP, CCG4 (Refer CY4541 kits hardware schematic) VBus OCP feature uses an internal ADC in the CCG to measure the voltage on the VBUS_MON input and uses the ADC output to detect over-voltage conditions.The default implementation of OVP uses firmware ISRs to turn off the FETs when OVP is detected. If quicker response is desired, there is the option of using a direct OVP_TRIP output derived from a hardware comparator associated with the ADC (SDK firmware do not enabled OVP_TRIP by default).

If you have been changed the way of OVP detection, for example, use external components to indicated OVP flag, you need initial a interrupt for OVP and change the OVP trigger event and callback. I do not recommend change it.

Best Regards,

Lisa

View solution in original post

0 Likes
2 Replies
Anonymous
Not applicable

Hi there

I am apologetic. I have never mention spec.

These are dual port and dual role.

0 Likes
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi Jason,

1. If you are not going to support HPI, what's you are process shall be follow Cypress HPI via I2C. For example, you need clear INT with I2C command. And then enter flash mode to upgrade firmware.

2. For OCP, CCG4 (Refer CY4541 kits hardware schematic) VBus OCP feature is implemented based on an external load switch and only uses a fault indicator GPIO coming into the CCG device. The default setting is VBUS_OCP_MODE == VBUS_OCP_MODE_EXT.

Since you are changed OCP hardware, please kindly change pin assignments in .cydwr file and change the OCP mode as per your hardware.

The MODE SDK have been defined @file pdss_hal.h:

#define VBUS_OCP_MODE_EXT               (0u)  /**< OCP through external hardware. */

#define VBUS_OCP_MODE_INT               (1u)  /**< Internal OCP without software debounce or hardware gate control. */

#define VBUS_OCP_MODE_INT_AUTOCTRL      (2u)  /**< Internal OCP with hardware gate control. */

#define VBUS_OCP_MODE_INT_SW_DB         (3u)  /**< Internal OCP with software debounce. */

#define VBUS_OCP_MODE_POLLING           (4u)  /**< Solution level polling based OCP. */

#define VBUS_OCP_GPIO_ACTIVE_LOW        (0u)  /**< GPIO low indicates fault condition. */

#define VBUS_OCP_GPIO_ACTIVE_HIGH       (1u)  /**< GPIO high indicates fault condition. */

3. For OVP, CCG4 (Refer CY4541 kits hardware schematic) VBus OCP feature uses an internal ADC in the CCG to measure the voltage on the VBUS_MON input and uses the ADC output to detect over-voltage conditions.The default implementation of OVP uses firmware ISRs to turn off the FETs when OVP is detected. If quicker response is desired, there is the option of using a direct OVP_TRIP output derived from a hardware comparator associated with the ADC (SDK firmware do not enabled OVP_TRIP by default).

If you have been changed the way of OVP detection, for example, use external components to indicated OVP flag, you need initial a interrupt for OVP and change the OVP trigger event and callback. I do not recommend change it.

Best Regards,

Lisa

0 Likes