TRAVEO™ T2G Forum Discussions

Hello Experts,

I was able to work with Evaluation board (TRAVEO II T2G KIT_B_E_LITE) which has MCU of CYT2BL5CAA using IAR workbench.

I used the T2G_Sample_Driver_Library_7.9.0\tviibe4m for initial configuration and i could see the LEDs are blinking.

I have a custom board which uses CYT2b95CAC chipset. I tried using the same configuration has of evaluation board(CYT2BL5CAA) and changed the only LED port pins, Flashing was successful but unfortunately no LEDs were blinking.

FYI.. I am using tviibe4m_flash_cm0plus_template from T2G_Sample_Driver_Library_7.9.0\tviibe4m\tools\iar\flash

My questions are 

1. Can i use the IAR workbench template of CYT2BL5CAA to CYT2b95CAC controller( both are dual core).

2. Is there any specific configuration i need to follow for this CYT2b95CAC.

3. I am suspecting Oscillator configuration needs to be tuned as in custom board we are using 20Mhz crystal whereas in evaluation board it was 16Mhz.

Thanks

Kiran

Hi expert.

Recently, I encountered a case where the SFlash of the CYT2B75CAS chip was abnormally modified;

The chip abnormality manifests itself in the form of failure to boot from power-up, connecting to the chip through the compiler Attach to running targe mode, and then reading the data in the SFlash area of the chip;

And compared with the other two normal chips, found that the abnormal chip SFlash area has a lot of data is not the same, the difference area is mainly in the paragraph Flashboot code and Patches; attached is the SFlash area data I saved, and the 3 chips are the same batch;

Rather strangely, the code does not contain any calls to the API interface for modifying the SFlash, only the Erase Code Flash and Work Flash code;

What could cause the SFlash area of the chip to be abnormally modified? Regarding the area 0x17001C00 ~ 0x17006FFF, can it be abnormally tampered with when the chip is in Normal mode?

Please help the experts to analyze the possible reasons why SFlash is being modified abnormally;

Thank you~~

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B7-SFlash-%E8%A2%AB%E5%BC%82%E5%B8%B8%E4%BF%AE%E6%94%B9/td-p/728079

SDL Ver: 7.9.0

jeon. Suppose there is an AAA with a 10ms cycle.
1. 40%delayed in the AAA message and sent to 14ms. (Can ID priority)
2. I think the next message will be sent after 10ms.
3. But the actual message was sent after 6ms.

Q1. In the case of above, is the CAN driver (SDL) sent message to 6ms to match the existing 10ms cycle?

Q2. Even if 40% delay occurs, can't i send the next message after 10ms?