TRAVEO™ T2G Forum Discussions

Hello Team,

I am LG India team,  

we are using I2C driver provided by Infineon team to LG Korea team,

in I2C driver, Cy_SCB_I2C_SlaveGetReadTransferCount( ) is available which Returns the number of bytes read by the slave since the last time Cy_SCB_I2C_SlaveConfigReadBuf() is called. 

we calling this function before Cy_SCB_I2C_SlaveConfigReadBuf().

but we found its not reading correct values.

could you test once share procedure to use.

We are looking for an MPU socket with below part number to use on a customer's prototype board.
・CYT4BFBDJS (272pin BGA)
Could you please tell me the supported socket part number of this MCU?

Thank you & Best regards,

顧客の試作基板上で使用するための、下記型番のMPUソケットを探しています。
・CYT4BFBxJSに (272pin BGA)
このMCUに対応するソケットの型番を教えて頂けますでしょうか？

よろしくお願い致します。

Hi Infineon team,

I'd run chip CYT3BB7CEBQ0AESGST using SDL 7.7.

I boot the CM0 chip using the Boot folder from SDL. 

Configure:

System init clock in file system_tviibh4m_cm0plus.c (sample with ECO=16MHz).

I using external crystal 8MHz (ECO = 8MHz). So I just changed CY_SYSTEM_PLLx_CONFIG_REFDIV, CY_SYSTEM_PLLx_CONFIG_FEEDBACKDIV, CY_SYSTEM_PLLx_CCONFIG_OUTDIV

to get PLL0 = 250 MHz

#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (4UL)

PLL1 = 196607999.92Hz

#define CY_SYSTEM_PLL1_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_INT (98UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_FRAC (5100273UL)
#define CY_SYSTEM_PLL1_CONFIG_OUTDIV (4UL)

PLL2 = 160MHz

#define CY_SYSTEM_PLL2_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL2_CONFIG_FEEDBACKDIV (40UL)
#define CY_SYSTEM_PLL2_CONFIG_OUTDIV (4UL)

PLL3 = 80MHz

#define CY_SYSTEM_PLL3_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL3_CONFIG_FEEDBACKDIV (80UL)
#define CY_SYSTEM_PLL3_CONFIG_OUTDIV (4UL)

Clock HFx:

Issues:

I use SDL API:

It seems to be OK. But when I run CM0 will reset and can't jump to CM7_0. 

If I reduce all PLL output clocks by half -> CM0 and CM7_0 run normally (but the clock is 1/2 smaller than desired)

If I use external crystal 16MHz and the default file system_tviibh4m_cm0plus.c things ok (CM0 and CM7_0 run normally).

Questions:

1. I think refdiv, feedbackdiv, and output are ok following the restrictions of the datasheet (Infineon-TRAVEO_T2G_CYT3BB_4BB-DataSheet-v09_00-EN.pdf).

But why chip can't run as expected?

2. Do I need to edit other values such as ROM/RAM waitstate and FLASH wait cycle?
If yes then what should the value be I can't find the reference.

Please help me to resolve these issues (Refer to file system_tviibh4m_cm0plus.c for more detail).

Thank you Infineon team.

Hello Infineon Team, 

ICU Elapsed time API is not reading properly during low frequency input signal. such as (10 HZ to 130 HZ) but the tick values are providing correctly for above 130 HZ input frequency Please find the configuration details here. 

Channel Tick Frequency -   8 MHZ of ICU Channel

Clock Reference Point Frequency - 16 MHZ

PClock frequency - 80 MHZ  

Kindly let me know is there any limitations in the input signal. or should I modifications in clock configurations?  

Hello,

We would like to use the low power mode of the CYT2B73. eco We have connected an external crystal of 16MHZ, do we need to connect an external low frequency crystal to the WCO pin and then configure it through software?

After checking the DEMO file for the MUC, it doesn't have WCO connected to it, but only the ECO pin does it enable low power mode?

For SLEEP and DEEPSLEEP mode what is the difference between the two?

If you go to low power, are the clocks all off and how do you wake up the MCU?

Above.

Thank you~

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B73%E7%9A%84%E4%BD%8E%E5%8A%9F%E8%80%97%E4%B8%8E%E6%97%B6%E9%92%9F%E6%99%B6%E6%8C%AFECO-amp-WCO/td-p/738107