SRAM Forum Discussions

I am using CY62167EV30LL, I want to share this memory between 2 microcontrollers. 

Query 1: can we share it? If yes, please suggest the solution.

I have thought to share half address line between the two microcontroller.

Other way around to mux the address line between the two controller and separate data lines for each controller.

Please suggest the solution.

Hi,

CY7C1168KV18 contain bidirectional data bus DQ.

The DQ port has build in serial termination but lack of active pull-up termination (for receiving mode).

The FPGA I'm using contain both termination (serial and  active pull-up termination).

The question is should I add external pull-up termination to the DQ bus?

(In AN4065 design example DQ doesn't have active pull-up termination)

Hello, in this post "https://community.infineon.com/t5/SRAM/QDR-IV-memory-controller-for-Zynq-Ultrascale/m-p/266947" infineon says that there is a internal controller for a single device.

I would like to use a single QDR-IV device but Vivado doesen't provide interface for CY7C4121KV13 18 bits wide.

Is it possible for infineon to share our controller or provide a third part that will provide us?

Regards

Simone

I think there are synchronous and asynchronous SRAM of Cypress, but I would like to know the main lineup of synchronous SRAM such as serial and parallel products.

Hello Infineon,

I'm conducting academic research in methods of reliability analysis with help of the 1021 SRAM series from Cypress, and I have a few questions:

1) Which test board is recommended for such work that is affordable but can accomplish the task?

2) Is there software or pre-developed code that could aid in this effort?

3) Is there a reliability report available for this technology for registered customers?

Thank you very much for your time,

Paul

This SRAM :CY62167EV30LL-45BVI is used in our product and no longer available. I appreciate your help to find a replacement for it.  Ideally a drop-in replacement and if not please advise on the options.

Assert CS(chip enable) and OE (output enable) pins
Is it possible to continuously read the data signal by switching the address signal? (Page Lead)

Hi,

CY7C1168KV18 has 16 pins for VDDQ and 10 pins for VDD.

In the recommended decoupling capacitors scheme (in AN4065) there isn't capacitor for each power pin.

Should  each power pin (Vdd, Vddq) get 100nF and 10nF decoupling capacitors?

Regarding VTT should each pullups get decoupling capacitor?

Best regards,

Erez