SRAM Forum Discussions
For CY7C1512KV18-300BZXC, is it comes in Tape and Reel packaging?
If yes, please let us know the Part in tape and Reel packaging and whether its available or not.
In one design we use the SRAM CY62167EV30LL-45BVXI with 65nm technology.
The data sheet CY62167EV30_MOBL_16_MBIT_1M_X_16_2M_X_8_STATIC_RAM.pdf says
"The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. "
A date is read from an address from the FLASH and this date is stored in the same address in the SRAM. Then the address will not be toggled.
Is it possible during this process that the SRAM goes into automatic power down?
How is the timing for the required address toggling defined?
The case would be very bad if the same address in the SRAM was written several times with different dates in succession. The SRAM is permanently chipselect with /CE1 and write is / WE controlled.
The last date is then not written because the SRAM has gone into power down due to the missing address toggling.
The SRAM can only be powered up again with a chip select /CE1=0 to 1 to 0.
Are 2 write commands possible in succession on this SRAM?
Hence my question about the time in ns at which the address must absolutely change so that the SRAM does not go into power down. This time is not in the data sheet. /CE1 is permanently low.
With best regards
Max Power
Hi there,
My engineering asked me a question about the fab-site description of marking code, please advise:
P/N: CY62167EV30LL-45BVXI
Where is the FAB SITE for code: F 04? in line 4
and where is for code: AB33?
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Dear Team,
Kindly let me know which is the best recommended DPRAM for new design and what is the life cycle of the same.
Previously I had used CY7C025-15AI for my design which is obsolete now.
Kindly let me know at the earliest.
Regards
Krishna
Show LessI searched everywhere however I can't find an IBIS file for 119pin PBGA that contains CY7C1062G30? There are IBIS files for every other device, but not 119pin PBGA.
Show LessHi,
Please share the IBIS MODEL FOR SRAM : CY7C1371KVE33-133AXI.
Any data/Test results to show that STK11C88-SF45TR can be used beyond its defined temperature range of 0 to 70 Degrees C?
I am looking for a drop in replacement for the STK11C88-SF45I part, I was not able to find any part except STK11C88-SF45TR. But the STK11C88-SF45TR has a operating temperature range of 0 to 70, I am looking for a
Does cypress have a memory controller IP for Xilinx's Zynq Ultrascale+ devices?
Hi Team,
We are going to propose "CY62148EV30LL-45ZSXIT" as a replacement for our current production renesas SRAM "RMLV0408EGSB-4S2#HA1". We need some parameter clarification
1. tOW - Output enable from write end (nS) , this timing parameter is not present in the cypress datasheet, in renesas datasheet its 5ns, Below is the image snipped from renesas datasheet where tOW is highlighted.
Could you please provide the timing of that parameter.
2. In capacitance, cypress datasheet provide as input and output capacitance as separate but in our current renesas part input and input/output capacitance is mentioned.
I want to know the input/output capacitance value, so that I can compare both the parts.
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