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Anonymous
Not applicable

 Hi

   

I'm working on interfacing cy7c1370d with spartan 6 fpga. In the data sheet its specified that the output buffers are tristated automaticaly during the 2nd cycle of the write operation where the data is presented on the DQ lines . but in the switching waveform of the datasheet at one clock transition the OE_n is high for half of the clock duration . Do i need to do the same while writing into the device ? please help...

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1 Solution
PriteshM_61
Employee

Hi Chaitu,

   

 

   

DQs/DQPs are tristated when -->  (WE# enabled) OR (Chip is disabled) OR (OE# is disable)

   

So, DQs/DQPs are automatically tristated during the data portion of a write cycle regardless of the state of OE# 

   

OR

   

you can have proper OE# level during the status change, like when status changes from read to write then OE# should be disable and from write to read OE# should be enable.

   

 

   

You can use both option according to your convenience.

   

I hope this clarifies your concern.

   

Thanks,

   

Prit

View solution in original post

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5 Replies
PriteshM_61
Employee

Hi Chaitu,

   

 

   

DQs/DQPs are tristated when -->  (WE# enabled) OR (Chip is disabled) OR (OE# is disable)

   

So, DQs/DQPs are automatically tristated during the data portion of a write cycle regardless of the state of OE# 

   

OR

   

you can have proper OE# level during the status change, like when status changes from read to write then OE# should be disable and from write to read OE# should be enable.

   

 

   

You can use both option according to your convenience.

   

I hope this clarifies your concern.

   

Thanks,

   

Prit

View solution in original post

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Anonymous
Not applicable

 Thank you prit for the reply 

   

and i had another problem in using the VHDL and Verilog model for CY7C1370D , when I initialize the memory as a component and instantiate it in my program with all the necessary inputs in xilinx , it gives an error in the model for illegal declaration in the sensitivity list for the clock validation process , can you suggest me how should i simulate the model without these errors ?

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PriteshM_61
Employee

Hi Chaitu,

   

 

   

Could you please be more specific about the error.

   

 

   

Thanks,

   

Prit

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Anonymous
Not applicable

problem with verilog model :'force statement not supported for synthesis' 

   

and for VHDL model it says : Line 231: Illegal name on the sensitivity list

   

the line 231 is :   WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);

   

These are the problems im facing while trying to use the model. ANy help is highly appreciated .

   

Thank you

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Anonymous
Not applicable

 I think i Found the problem i was trying to syntehsize the model which is a wrong thing to do . It has to be used in the simulation (testbench)  . 

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