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PSoC Creator & Designer Software

Anonymous
Not applicable

Can i use any Component in my verilog code by instantiating it?

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6 Replies
HeLi_263931
Honored Contributor II

I think you can only instantiate component which are defined in Verilog themselves. This should everything defined as 'primitive'.

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Anonymous
Not applicable

So, I can instantiate only components with .v file, right?

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HeLi_263931
Honored Contributor II

Yes.

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Anonymous
Not applicable

Please, help me with this. I'm trying to instantiate "cy_dffe_v1_0" just for a example and i'm getting this error:

   

 

   

"M0120:Can't find 'cy_dffe_v1_0" in library 'work' with path 'lcpsoc3'.

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HeLi_263931
Honored Contributor II

the DFFs are defined in rtl.v, as

   
module cy_dff (d, clk, q);
   

So maybe you want to include that one? (The definition of cy_dffe_v1_0 is empty, if you look at the file...)

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Anonymous
Not applicable

That's true. 

   

Thank you for your help.

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