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PSoC 6

BeBl_4528851
New Contributor II

I'm working through the PSoC 6 MCU Programming Specifications (Rev-L), adapting the PSoC4 HSSP example for the PSoC 6.

I am looking for help related to the SWD_Write() and SWD_Read() implementation.

The details of these functions are not included in the psuedo code, only a quick summary in Table 4-1:

Header 1Header 2Header 3
SWD_Write

IN APnDP, IN addr, IN data32,

OUT ack

Sends a 32-bit data to the specified register of the DAP using SWD interface. The register is defined by the “APnDP” (1 bit) and “addr” (2 bit) parameters. The DAP returns a 3-bit status in “ack”.
SWD_Read

IN APnDP, IN addr,

OUT data32, OUT ack, OUT parity

Reads 32-bit data from the specified register of the DAP using SWD interface. The register is defined by the “APnDP” (1 bit) and “addr” (2 bit) parameters. DAP returns a 32-bit data, status, and parity (control) bit of the read 32-bit word.

I do not see where the actual values that SWD_Write() and SWD_Read come from for these registers.

  • What values should I use for these macros, or where can I find this information clearly?
    • When I look at the PSoC 4 HSSP code example, I don't see a clear mapping between the APnDP and Address values given in the PSoC6 Programming Spec and the values used for the PSoC 4 HSSP examples.

Macro Name Used in PSoC6 Programming Specs
IDCODE
ABORT
CTRL/STAT
SELECT
RDBUFF
CSW
TAR
DRW
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BeBl_4528851
New Contributor II

I believe I've been able to answer my question based on the information here: Introduction to Cortex Serial Wire Debugging - ImProgrammer - 博客园

This results in the following macros. These are sent LSB first, so I included the bitstream in the order I'd expect to see on the logic analyzer.

/* Macro Definitions for Debug and Access Port registers read and write Commands

   used in the functions defined in UpperPacketLayer.c */

#define CTRLSTAT_READ       0x8D //LSB First Time Series: 10110001

#define IDCODE_READ         0xA5 //LSB First Time Series: 10100101

#define CSW_READ            0x87 //LSB First Time Series: 11100001

#define TAR_READ            0xAF //LSB First Time Series: 11110101

#define DRW_READ            0x9F //LSB First Time Series: 11111001

#define CTRLSTAT_WRITE      0xA9 //LSB First Time Series: 10010101

#define SELECT_WRITE        0xB1 //LSB First Time Series: 10001101

#define CSW_WRITE           0xA3 //LSB First Time Series: 11000101

#define TAR_WRITE           0x8B //LSB First Time Series: 11010001

#define DRW_WRITE           0xBB //LSB First Time Series: 11011101

#define IDCODE_WRITE        0x81 //LSB First Time Series: 10000001

#define ABORT_WRITE         IDCODE_WRITE

I will update the SWD_Read/Write() functions to use these full 32-bit addresses, instead of implementing them with the separate APnDP/addr values.

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BeBl_4528851
New Contributor II

To clarify:

The PSoC 4 HSSP Example SWD_Read/Write simply take the address as a 32-bit value.

The PSoC 6 Programming Specifications document breaks this out as a separate APnDP and Address(2-bits).

I do not know how to map the PSoC 6 format to the actual 32-bit value that the SWD_Read/Write should send.

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BeBl_4528851
New Contributor II

I believe I've been able to answer my question based on the information here: Introduction to Cortex Serial Wire Debugging - ImProgrammer - 博客园

This results in the following macros. These are sent LSB first, so I included the bitstream in the order I'd expect to see on the logic analyzer.

/* Macro Definitions for Debug and Access Port registers read and write Commands

   used in the functions defined in UpperPacketLayer.c */

#define CTRLSTAT_READ       0x8D //LSB First Time Series: 10110001

#define IDCODE_READ         0xA5 //LSB First Time Series: 10100101

#define CSW_READ            0x87 //LSB First Time Series: 11100001

#define TAR_READ            0xAF //LSB First Time Series: 11110101

#define DRW_READ            0x9F //LSB First Time Series: 11111001

#define CTRLSTAT_WRITE      0xA9 //LSB First Time Series: 10010101

#define SELECT_WRITE        0xB1 //LSB First Time Series: 10001101

#define CSW_WRITE           0xA3 //LSB First Time Series: 11000101

#define TAR_WRITE           0x8B //LSB First Time Series: 11010001

#define DRW_WRITE           0xBB //LSB First Time Series: 11011101

#define IDCODE_WRITE        0x81 //LSB First Time Series: 10000001

#define ABORT_WRITE         IDCODE_WRITE

I will update the SWD_Read/Write() functions to use these full 32-bit addresses, instead of implementing them with the separate APnDP/addr values.

View solution in original post

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