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PSoC 6

JaMe_3934746
New Contributor II

I have used BLE on CM4 & other system including ADC & 2 UART on CM0+ core for my application.

When i move CM4 in deep sleep & keep CM0+ halted then it works fine, CM4 stays in deep sleep until i give GPIO interrupt to wake up & start BLE.

But if i use CM4 & CM0+ parallel at that time CM4+ continuously wakes up & sleep down.

Can i have any clue for this ?

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1 Solution
JaMe_3934746
New Contributor II

yes, First of all i checked that file, There is no any Interrupt is assigned to both the core.

For CM4 BLE switch (GPIO interrupt) is wake up source And

For CM0+ Digital Input(GPIO interrupt) & Watch dog interrupt is wake up source.

If i puut while(1); after enabling CM4 in main() of CM0 file, it works fine(CM4 keeps in deep sleep until GPIO interrupt).

View solution in original post

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3 Replies
Yugandhar
Moderator
Moderator

Hello,

Please check the interrupts tab in the design-wide resources window (.cydwr file) and see if the interrupts are allocated to both the CPU cores(CM0+ and CM4) in the ‘ARM CMx Enable’ checkbox in PSoC Creator.

Thanks,

P Yugandhar.

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JaMe_3934746
New Contributor II

yes, First of all i checked that file, There is no any Interrupt is assigned to both the core.

For CM4 BLE switch (GPIO interrupt) is wake up source And

For CM0+ Digital Input(GPIO interrupt) & Watch dog interrupt is wake up source.

If i puut while(1); after enabling CM4 in main() of CM0 file, it works fine(CM4 keeps in deep sleep until GPIO interrupt).

View solution in original post

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Yugandhar
Moderator
Moderator

Hello,

It is recommended to enable the CM4 in CM0+ file and use the infinite loop for CPU core. Can you please share your project ?

Thanks,

P Yugandhar.

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