PSoC™ 6 Forum Discussions

modus example CTBM and UDB  secure boot

  Manager ，选型的时候发现， CTBM 、UDB、securereboot 这些功能，选型的时候我想更深入了解，

有更多资料吗 ？

moudus 没有相关例程 参考；其他的像 capsense  crypto   等都有例程，我也理解，上述功能用的较少，有的客户比较较真，想了解更多

Help

Thanks

What logic components from Infineon can run directly from a standard 1.5v battery, taking into account that the battery voltage can drop down to 1.2V?

PSoCs  operate down to 1.7V and XMCs operate down to 1.8V. Some PSoC MCUs have option for thier core to run down to 0.9V internally. PSoC memory retention appears to operate down to 1.4V via external Vbatt.

Are there Low Power MCUs in Infineon's lineup, (PSoC, XMC or other), that are designed to operate down to 1.2V?

What is the lowest voltage battery that Infineon recommends each of their Low Power MCUs can directly operate from?

Greg

 can I program my application code into CY8CPROTO-062-4343W using using external FTDI (FT232RL USB to TTL) using MODUS toolbox.

Hello,

I am new to PSOC6. I have been trying to get the UART running by following the instruction given in the YouTube tutorial(https://www.youtube.com/watch?v=ZJOF2f423nI&list=PLIOkqhZiy83H81AhLcjwIKkB9w07JQZS6&index=5).

I am not getting smooth output, rather a gibberish output in the beginning and some random spaces are appearing in the output as shown below:

stdio_user.h file has been modified as demonstrated in the tutorial and my main program is in CM4 as shown below:

Is there anything that I am missing here?

I would be glad if you could provide some solution to this as it is very urgent.

@Yugandhar 

Thanking you,

Anik Sengupta

Hello, I'm unable to build the examples "OTA_Using_HTTPS" and "OTA_Using_MQTT" using MTB 3.0.  I have tried BSP "CY8CPROTO-062-4343W" and "CY8CEVAL-062S2-LAI-4373M2".  The error happened during the linking step:

ModuleNotFoundError: No module named 'cryptography.hazmat.primitives.asymmetric.ed25519' 

There were also some compile warnings.  Please find attached logs.

Thank you!

Hello,

For the project that we are working on we are using the TRNG inside the CY8C6347 to generate some values (AES initialization vectors for example) on a somewhat regular basis and want to make sure that the numbers that are generated are valid.

In reading the TRM it describes two "health monitor" capabilities that are built into the hardware, however looking at the PDL implementation it does not appear that this functionality is being enabled. Is there a reason for not having this enabled? If we were to implement our own code based on `Cy_Crypto_Core_V1_Trng()` are there any suggested starting points for the counters and window size to use for the health checks?

Also on a related note the PDL is enabling/disabling the TRNG for each operation. I'm guessing this is to help reduce power consumption as the TRM indicates that the ring buffers that make up TRNG "consume a significant amount of power" but there is no value in the datasheet indicating how much power the TRNG consumes. Is there a nominal power consumption value that we can use to determine if it is better for us to be enabling/disabling the TRNG for each 32-bit value or if it would be better to generate multiple 32-byte values in succession without disabling the TRNG after each one.

Thanks,

Nate

Hi I'm working with the EVK: CY8CKIT-064S0S2-4343W

I'm using Modustoolbox 3.0 I've started a new application from example UART_Transmit_and_Receive for CY8CKIT-064B0S2-4343W and migrated it for CY8CKIT-064S0S2-4343W using this guide:

https://community.infineon.com/t5/PSoC-6/How-to-run-examples-of-peripheral-on-CY8CKIT-064S0S2-4343W/m-p/356686
I've compiled the project successfully 

I've programmed the PSOC and this is the log:

Open On-Chip Debugger 0.11.0+dev-4.4.0.2134 (2022-09-08-13:07)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
kitprog3 set_latest_version: X:/Infineon/Tools/ModusToolbox/tools_3.0/fw-loader 2.40.1241
** Main Flash size limited to 0x1D0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm4_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
Info : Using CMSIS-flash algorithms 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm4' (footprint 12780 bytes)
Info : CMSIS-flash: ELF path: ../flm/cypress/cat1a/CY8C6xxA_SMIF_S25FL512S.FLM
Info : CMSIS-flash: Address range: 0x18000000-0x1BFFFFFF
Info : CMSIS-flash: Program page size: 0x00001000 bytes
Info : CMSIS-flash: Erase sector size: 0x00040000 bytes, unified
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf155, serial=160C19A4002A9400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.40.1241
Info : KitProg3: Pipelined transfers enabled
Info : KitProg3: Asynchronous USB transfers enabled
Info : VTarget = 3.319 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
***************************************
** Use overriden Main Flash size, kb: 1856
** Silicon: 0xE4A0, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CYS0644ABZI-S2D44
** Flash Boot version: 4.0.1.1089
** SFlash version: 0x4bbb0
***************************************
Info : gdb port disabled
Info : starting gdb server for psoc64.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
Info : SWD DPIDR 0x6ba02477
Info : kitprog3: acquiring the device (mode: reset)...
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : Waiting up to 15.0 sec for the handshake from the target...
Info : [psoc64.cpu.cm4] external reset detected
psoc64.cpu.cm4 halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x1600400c msp: 00000000
** Programming Started **
auto erase enabled
Info : Flash write discontinued at 0x1002cf53, next section at 0x10050000
Info : Padding image section 0 at 0x1002cf53 with 173 bytes (bank write end alignment)

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Info : Padding image section 1 at 0x100591f2 with 14 bytes (bank write end alignment)

[100%] [################################] [ Erasing ]

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wrote 221696 bytes from file X:/mtw/UART_Transmit_and_Receive/build/CY8CKIT-064S0S2-4343W/Debug/mtb-example-psoc6-uart-transmit-receive.hex in 3.124608s (69.289 KiB/s)
** Programming Finished **
** Program operation completed successfully **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : [psoc64.cpu.cm4] external reset detected
shutdown command invoked
Info : psoc64.dap: powering down debug domain...

1. I don't understand what this error means: Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!

2. After programming I'm observing the COM port of the KitProg and what I see is this:

[INF] /******************************************************/
[INF] PSoC6 CyBootloader Application 1.1.0.1796
[INF] /******************************************************/
[INF]
[INF] CypressBootloader Started
[INF] Secondary Slot 2 will upgrade from External Memory
[INF] Enabled multi-image N = 2:
[INF] External Memory initialized w/ SFDP.
[INF] Swap type: none
[INF] Swap type: none
[ERR] Image in the primary slot is not valid!
[INF] CypressBootloader found none of bootable images
[ERR] There is an error occurred during bootloader flow. MCU stopped.

Why the MCU doesn't boot from the primary slot?

Why the MCU secondary slot is not erased? What is this program?

Thanks

Michael H. 

Hi!
I work on my MTB projects in VS code. I am able to use an instance of modus shell separate from my vs code instance containing my project.

Instead, I would like vs code to know the path to modus shell. I naively added the path to my settings.json file, which is the configuration file, as such:

    "terminal.integrated.profiles.windows": {
        "Modus": {
            "path": "C:\\Users\\jcbsk\\AppData\\Roaming\\Microsoft\\Windows\\Start Menu\\Programs\\ModusToolbox 2.2\\modus-shell 1.1.0.lnk"
        }
    },

 But this causes an error:

The terminal process failed to launch: A native exception occurred during launch (Cannot create process, error code: 193).

Any way I can achieve my goal? Thanks!