PSoC™ 6 Forum Discussions

Hi,

I am working on PSOC6 CY8C MCU in one of our projects and we want to secure the debug port in NAR.

I am able to lock the debug port (CM0+ and CM4) by configuring sFlash NAR area(0x16001A00), we used  Cy_Flash_WriteRow() system call to write into sFlash NAR area.

Now I have some queries which are mentioned below:

1. How to unlock the debug port (CM0+ and CM4) in NAR so that I can re-program new firmware?

2. If it's not possible to unlock the debug port via firmware, is there any other way to do it?

Thank you.

Hi,

We are seeing a positive pulse in pin 6.5 while powering up, resetting & programming (via SWD). Please see the attached screenshots. 

The pin is port 6, which also has SWD and reset lines. We tested the pin with various configurations via PSoC creator, but couldn't find out the root cause. Can anyone help us in debugging this issue ?

Edit: We are also seeing a similar issue in pin 11.1

regards,

Vinu

@shibin 

I am using CY8C6244AZI-S4D93 MCU with the above device configurator settings for clocking.

I have an external oscilator that is 12Mhz going into the EXTCLK of the system and being used as the source for both PLL and FLL. PLL is used to generate the main system clock.

My goal is to output a 15Mhz signal on the External Clock pin P0[5]. I have a PCB with this pin exposed and i have been using a 500MS/s logic analyzer to measure the frequency of this clock.

I have the FLL configured to generate a 60Mhz clock, and then using a /4 divider in the CLK_HF1 block the tool shows me that i get 15Mhz. However when i measure this on P0[5] i only get 3Mhz or 1/4th of my input EXTCLK. If i set the divider of CLK_HF1 to 1 i get the 12Mhz on the output, not the 60Mhz from the FLL. There is no configuration that seems to get me 15Mhz from the FLL on the CLK_HF1 output pin.

This seems to be a bug but im not sure where to look to figure it out since this is all the configurator tool.

Note: this is Device Configurator 4.0.0.748 and 3.0 tools.

Edit 1: After tons of debugging i found the issue. I used Cy_SysClk_FllGetConfiguration() in CM4 main and when i checked it the outputMode was set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT which is bypassing the FLL. Eventually after jumping around a bunch the issue was "Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)" call in CM0 core. This disabled the FLL output along with a few other things. Taking that out got me my 15Mhz on pin  P0[5]

Posting here as an update in case someone runs into something like this in the future.

Hi,

I implemented DFU BLE in MTB for PSOC6 with CRC app verify.

I want to enable signature verification like SHA256 encrypted with RSAES-PKCS.

Do an example exists ? How I can enable this functionnality ?

Thank you for your support,

Kind regards

Hello,

In one of my files I have a while-loop which puts an array into the UART using Cy_SCB_UART_PutArray() and in another file I am receiving it with  a while-loop using Cy_SCB_UART_GetArray().

Cy_SCB_UART_PutArray(UART_HW, buffer, sizeof(buffer));
Cy_SCB_UART_ClearTxFifoStatus(UART_HW, CY_SCB_UART_TX_NOT_FULL);

Receive

uint8_t rxBuffer[5];
cy_rslt_t result;

result = Cy_SCB_UART_GetArray(UART_HW, &rxBuffer, sizeof(rxBuffer));

    if(result != CY_SCB_UART_RX_NO_DATA)
    {
        for(int i = 0; i < sizeof(rxBuffer); i++)
        {
            printf("%c\r\n", (char) rxBuffer[i]);
        }
    }

Hello Everyone,

I'm trying to use PDL library in my project but it's not appearing in PSOC4 creator workspace

I can check it under Help -> Documentation.

I also tried with different version and changing path in tools -> options tab but unable to use PDL with development kit

CY8Ckit-147 PSCO 4100

If i use any PSOC6 chip for test, then PDL is accessbar with PDL 3.1.5 version but not for PSOC4 with any 2.0xx version.

If anyone has an idea then please share with me.

Thank you .

Dear Team,

Do you have a PSoC64 (CYB06447BZI-BLD53 preferred) BSP example for the ModusToolbox 3.0?

Regards,

Gintaras

Is there any documentation on the Table of Contents2 (TOC2) beyond what is in "AN221111 PSoC 6 MCU designing a custom secured system"?  I'm specifically interested in how userKeyAddr is used.  userKeyAddr should point to a 1k block of flash that has space for 4 keys, but I can't find anything on what these keys are.

Hi, I'd like to know is it right?

When I change bsp mcu target, from default CY8C6244LQI-S4D92 to CY8C6244AZI-S4D93, I can program the kit successfully.

I was expected an error from programmer tool. I'm using ModusToolbox 3.0.

In .hex file how can I check there is right metadata?

Hi, 

Understand that this example project "PSoC 6 MCU with BLE Connectivity: Battery Level (FreeRTOS)" works with PSoC 6 BLE Prototyping Kit (CY8CPROTO-063-BLE) EVK - and it is currently working with ModusToolbox version 2.x, does this example project support ModusToolbox software version 3.0? If not, any plan to bring-up this project to support latest ModusToolbox version 3.0? 

Thank you.