PSoC™ 6 Forum Discussions
PSoC 6 BLE Prototyping Board Guide, Doc. # 002-24993 Rev. *A says
Connect the Prototyping Board to the PC through the USB Micro-B Connector (J8) as shown in
Figure 3-2. The kit enumerates as a composite device. If you are plugging in the PSoC 6 BLE
Prototyping Board to your PC for the first time, the kit drivers will get installed automatically.
Is there any other way to install the kit drivers? We're thinking of buying the CY8CPROTO-063-BLE, but want to explore it in PSoC Creator first, to make sure it meets our needs.
Show LessI am following "Snippet 2: PDM/PCM Asynchronous Receive" from the link below:
https://cypresssemiconductorco.github.io/psoc6hal/html/group__group__hal__pdmpcm.html
The pdm_pcm_event_handler never gets called but when I comment out the line below it starts working.
Hi,
I have a PSoC 6-BLE Pioneer Kit (CY8CKIT-062-BLE). I would like to display the status of PSoC6 with (TeraTerm) on the UART of the PC, but I would like to display it using the BluleTooth (BLE4.2) built into the PC instead of using the dongle. Is there any samplea close to this?
Especially for the development on the PC side, it would be helpful if you could give me advice on whether to take the same approach.
Thanks,
Kenshow
Hi.
In cyhal_i2c_master_read() (and cyhal_i2c_master_write()), a failure returned by Cy_SCB_I2C_MasterSendStart() (or Cy_SCB_I2C_MasterSendReStart()) will cause the value returned by cyhal_i2c_master_read() not to be a legal cy_rslt_t.
Cy_SCB_I2C_MasterSendStart() returns a cy_en_scb_i2c_status_t, and if this value is anything other than CY_SCB_I2C_SUCCESS, it will become the return value of cyhal_i2c_master_read(), which is defined as returning a cy_rslt_t.
cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop)
{
if (_cyhal_scb_pm_transition_pending())
return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK;
/* Start transaction, send dev_addr */
cy_en_scb_i2c_status_t status = obj->context.state == CY_SCB_I2C_IDLE
? Cy_SCB_I2C_MasterSendStart(obj->base, dev_addr, CY_SCB_I2C_READ_XFER, timeout, &obj->context)
: Cy_SCB_I2C_MasterSendReStart(obj->base, dev_addr, CY_SCB_I2C_READ_XFER, timeout, &obj->context);
if (status == CY_SCB_I2C_SUCCESS)
{
while (size > 0) {
if (size == 1)
{
ack = CY_SCB_I2C_NAK;
}
status = Cy_SCB_I2C_MasterReadByte(obj->base, ack, (uint8_t *)data, timeout, &obj->context);
if (status != CY_SCB_I2C_SUCCESS)
{
break;
}
--size;
++data;
}
}
if (send_stop)
{
/* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */
/* each block, otherwise it may break the transmission */
Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context);
}
return status;
}
-Nick
Show LessHi,
I've selected a New Application for PSoC 6 Wi-Fi BT Prototyping Kit and I selected GPIO_Interrupt. After the project is created I see only one project. Where is the project for CM0? As far I know PSOC62 always require two project on for CM0 and one for CM4.
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Hello,
I am learning PSoC6 from the PSoC6 101 video tutorial series . From the PSoC 6 - 1-1-Introduction Alan Hawse told that PSoC6 chapters contains 4 parts.
I have downloaded the 1st,2nd and 3rd parts. And the last part is "connecting with WiFi & Cloud services".And I do not know the hyperlink of it. How can I get it?
Thanks in advance.
I've been trying to get my BLE over-the-air (OTA) device firmware update (DFU) to work. My bootloader is just a stripped down version of the CE16767 example code. I am fairly sure that it is working right because CySmart has no problem downloading my code and then after the download the system gets through the soft reset all the way the call to SwitchToApp(stackPointer, resetHandler) in Cy_DFU_SwitchToApp(uint32_t appId). The system then seems to lock up in the assembler code in Cy_DFU_SwitchToApp.
In Cy_DFU_SwitchToApp, stackPointer gets set to 0x08008000, which just doesn't seem right. To the best of my understanding, 0x08008000 is the starting address of core1 of the bootloader and the stack start for the main app should be at the end of the ram allocated to App1.
So my best guess is that I've somehow botched the updates I had to make to the 4 dfu_cm*.ld linker scripts. I have attached those scripts. Can anybody spot anything I bungled in them? Or do they look like they should be fine as is and I should look elsewhere?
Thanks for any and all help,
Ed H.
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I'm trying to adapt this code example to our design requirements. We are currently running this code example on PSoC 6 BLE prototyping kit (CY8CPROTO-063-BLE). I've switched the BLE stack to running on Cortex M0+ following the instructions and changed the toolchain to MDK. However we encounter HardFault during App2 startup, in the Cy_BLE_Start function. Our observations are:
- This issue does not occur when using ARM-GCC toolchain
- App1 (DFU mode) works properly
- With the debugger we were able to trace down the HardFault to function Cy_BLE_StackInit, and from the stack frame the PC register address when the fault occurred belongs to the function CyBle_RcbRegRead
0x10016588 0x00000028 Code RO 10367 i.CyBle_RcbRegRead cy_ble_stack_mdk_controller_soft_cm0p.a(CyBleRcb.o)
Any help would be appreciated. Thanks!
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I'm trying to implement something like this: Preserving debugging breadcrumbs across reboots in Cortex-M on CM4 in a CY8C6347BZI-BLD53. However, I'm unsure about where I can safely carve out a piece of RAM for saving breadcrumbs. If I look at cy8c6xx7_cm0plus.ld I see:
ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000
but in cy8c6xx7_cm4_dual.ld I see:
ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800
So, I have two ranges:
0x08000000 - 0x08023FFF
and
0x08024000 - 0x080477FF
There is also this comment in cy8c6xx7_cm4_dual.ld:
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
I am using dual-core BLE, so I have to be careful not to step on that.
So, I started looking at saving data in flash. That looks like a great option. There is lots of room in even one row of sflash_user_data to store a whole cy_stc_fault_frame_t and whatever else I can think of. And, it should persist across power off. However, I am concerned that I can only write to flash by calling Cy_Flash_WriteRow. If I am dealing with a Hard Fault, maybe the stack is corrupted. Can I still call a function? I guess if the fault occurs while the Processor Stack Pointer (PSP) is active, the fault handler will run with the Main Stack Pointer (MSP), and I should be OK. (I'm running FreeRTOS.) But, what if the fault occurs in an Interrupt Service Routine?
Maybe the best option is all of the above, a RAM save area plus a flash row... if I can figure out where to put the RAM area.
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I'm using psoc6-wifi-bt (CY8CKIT-062-WiFi-BT) , Any Cloud MQTT Client to connect to IBM cloud so does MQTT client in modus toolbox uses SNI(server name indication)? Would appreciate help.....
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