PSoC™ 6 Forum Discussions
Hi all. I'm having a problem with the Cy_SCB_UART_PutArrayBlocking function. This is with the BLE pioneer wifi, kit2. I can trace through all the sub functions with the debugger, and it looks like everything is working correctly, but nothing gets written from the UART. I am able to receive data with no problem though. Here is my setup - is there something more I need?
init_status = Cy_SCB_UART_Init (UART_HW, &UART_config, &UART_context);
if (init_status != CY_SCB_UART_SUCCESS) {
do {
Cy_GPIO_Inv (LED_Red_P0_3_PORT, LED_Red_P0_3_NUM);
CyDelay (50);
} while (true);
}
Cy_SCB_UART_Enable (UART_HW);
// Unmasking only the RX fifo not empty interrupt bit
UART_HW->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
Cy_SysInt_Init (&UART_SCB_IRQ_cfg, &ISR_UART); // Interrupt Settings for UART
NVIC_EnableIRQ (UART_SCB_IRQ_cfg.intrSrc); // Enable the interrupt
__enable_irq (); // Enable global interrupts.
The interrupt handler works as expected. After receiving a command to send data:
if (bExecute) {
// Process the data through the CFFT/CIFFT module
arm_cfft_f32 (&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse);
// Process the data through the Complex Magnitude Module for
// calculating the magnitude at each bin
arm_cmplx_mag_f32 (testInput_f32_10khz, testOutput, fftSize);
// Calculates maxValue and returns corresponding BIN value
arm_max_f32 (testOutput, fftSize, &maxValue, &testIndex);
if (testIndex == refIndex) {
Cy_SCB_UART_PutArrayBlocking (SCB5, testOutput, fftSize);
// Blocking wait for transfer completion
while (!Cy_SCB_UART_IsTxComplete (SCB5)) {}
}
As I said, the last line above completes, the system thinks all the data was sent properly, but nothing is sent.
I had this working in a previous project, but the difference is that there I was using high level UART functions.
There seems to be some confusion about that. In the UART data sheet it clearly says that high level functions are to be used when the interrupt mode is internal, and low level when the mode is external. However the example code shows using low level functions with the internal mode. I am using internal mode, and indeed it works, for receiving data. Also, the high level example code shows using Cy_SCB_UART_PutArrayBlocking, even though it is supposed to be a low level function! The PDL definitely states not to mix the low and high level functions. So it is confusing.
Should my code work? If not, why.
Thanks, Russ
Show LessI've been studying code examples from the PSoC6 101 tutorial, along with the code for the BLE throughput example. I noticed that two different connection events are used, CY_BLE_EVT_GAP_DEVICE_CONNECTED, and CY_BLE_EVT_GATT_CONNECT_IND. What is the difference between these two events and does it matter which one I use to indicate the completion of a Bluetooth connection?
- Jason O
Show LessHello, community!
I have a 128x64 pixel graphic LCD panel with a ST7290 controller and I want to connect it to a PSoC 6. I understand that there are voltage levels, but I plan to use logic voltage converters to get around the problem. I plan to use serial communication mode, so that 3 GPIOs should be enough.
I would like to know if anyone has done this before, so that I could get a code example to start off. Anyone?
Thank you very much.
Júlio Tanomaru, from Brazil
Show LessDear all,
I want to create project in ModusTollBox with projector creator 1.2, but always report issue as follows:
---------------------------------------------------------------------------------------------------------------------------------------------------
Project creation command to be executed:
C:/Users/Bill/ModusToolbox/tools_2.2/project-creator/project-creator-cli.exe --board-id CY8CPROTO-062-4343W --board-uri https://github.com/cypresssemiconductorco/TARGET_CY8CPROTO-062-4343W --board-commit latest-v2.X --app-id mtb-example-anycloud-mqtt-client --app-uri https://github.com/cypresssemiconductorco/mtb-example-anycloud-mqtt-client --app-commit latest-v2.X --user-app-name AnyCloud_MQTT_Client --target-dir C:/Users/Bill/mtw/CY8CPROTO-062-4343W --output-for-machine --use-modus-shell
Getting manifest...
Processing super-manifest https://github.com/cypresssemiconductorco/mtb-super-manifest/raw/v2.X/mtb-super-manifest-fv2.xml...
Download of https://github.com/cypresssemiconductorco/mtb-super-manifest/raw/v2.X/mtb-super-manifest-fv2.xml failed: Connection timed out
Failed to get the information.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
I exec many times with this process , but can not create project successfully.
Could you help me?
Thanks
Show LessHello,
I am working on a project and found that the PSoC 6 Wi-Fi BT Prototyping Kit (CY8CPROTO-062-4343W) meets all of my requirements. The issue I am having is that the LBEE5KL1DX is unavailable. I know it is based on the CYW43438WKUBGT but that has a M3 core built in, which I do not need as I am interfacing with the CY8CMOD-062-4343W (though I have been unable to find a footprint and PCB lib). I like the CY8CMOD-062-4343W because of the core M0 + M4 processors. I am receiving data from 7 different CYBLE-416045-02 Bluetooth modules (also core M0 + M4) and then forwarding that data to a PC via WiFi. Is there a replacement for the LBEE5KL1DX or possibly another combination that would work for my application?
Show LessHi,
I'm relatively new to microcontrollers and was wondering whether it is possible to connect both the EINK and an external sensor to the main board, since the EINK display takes all the space on the board. Most importantly, I need the Vin, SDA SCL ports freed.
Thank you in advance.
Show LessI found that when I set a GPIO drive mode to resistive pull up/down the voltages are 2.5V high, and 1V low.
In strong drive mode setting the pin high is correct at 3.3V and low correct at 0V.
With drive mode set to resistive pull down I see 3.3V high, 1V low
With drive mode set to resistive pull up I see 2.5V high, 0V low
Any idea why this is happening? I would like to use resistive pull up/down drive mode and have the gpio output 3.3V and 0V when I set it high or low
I am using CY8C6347LQI-BLD52 pin P7.2
Show Less
Hello Cypress,
Jumping ahead: The profanities and curses were many when I discovered the cause.
I'm a long time user of the PSoC5LP family - great chips. So I am no beginner to this or Creator. Two days ago I bought a CY8CKIT-062-BLE HWv.B and I am in the process of building a prototype to a tight deadline that the PSOC63 will interface to analogue and digital, so I have adequate levels of pressure already with a new design, new circuitry, new PSoC architecture and firmware. Hence the eval board so to reduce my mental workload - one less thing to concern myself with. The out-of-the-box E-ink and BLE demo ran perfectly so I was assured the board was good. I updated the kitprog version.
I am running all the latest software, Creator 4.4, PDL 3.1.4, wrote my code to generate a synchronised voltage and IO bitstream - compiled and programmed successfully and yet nothing. Strange, so I spend the next day going over documentation and various code examples. Thoroughly miserable I started re-watching Alan's PSoC6 101 videos in case I missed something, good videos - I still couldn't get the board to do anything. I had updated all the components because they were out of date and caused compile problems using potted examples. I can't even blink a F*c£!ng LED!. The test equipment is out and I'm methodically going through everything - the very simple code should work and does on PSoC4 and PSoC5LP eval boards and boards that I have designed - am I going mad? What am I doing wrong?
Two days I have wasted on this and the solution was to use an earlier version of PDL v3.0.1. I then found articles on here that confirmed what I discovered: thanks to MotooTanaka, - I have until now to encounter an issue with PDL versions.
In the beginning, I checked the documentation and it states operation with versions 3.0.1+ and this is on the product page. I was miffed to get an earlier version of the board and will not be able to use MODUS Toolbox in future - I've tried it with another board and I prefer Creator anyway.
There is no mention of the PDL version issues on the product page and I bought the board to save me time and heart-ache, but you severely disappoint on this occasion - what were you thinking? The board is selected as the target in Creator
why did you not include a warning that the PDL is incompatible rather than warn that component versions are out of date, need updating, successfully compile and program - only to DO NOTHING, but cause unnecessary debugging?
I understand older revisions of boards can resurface in distributors inventory, I bought mine from RS, but versions of software and hardware MUST work as advertised.
In conclusion:
1. Software and hardware MUST work as advertised.
2. To save others unnecessary debugging and stress please update the product page to reflect the reality of compatible software and hardware versions. USE PDL v3.0.1
3. An apology and a later revision of the eval board would go some way to making up for this.
An annoyed, disappointed and yet slightly relieved to have a way forward
Matthew
Show Less
Device - CYBLE-416045-02
We are developing a BLE solution by using module CYBLE-416045-02 with several security features implemented by a external Trust-M through I2C communication. Besides, we use syspm to achieve power saving by making core m0+ and m4 go to deepsleep.
Unfortunately, we now bumping into a issue that i2c seems not working after m4 back to active. From LA displaying, we saw vcc and rst pins not pulled-high.
Anyone knows that any case can prevent I2C working in case of low power management?
Main flow
1. m0+ start itself and start BLE and m4 core.
2. m0+ going to deepsleep and process BLE events
3. m4 setup initialization (SAR, TCPWM, EEPROM, Trust-M & I2C, BLE)
4. ( main infinite loop ) m4 calls syspm to transit to deepSleep mode
5. ( main infinite loop ) m4 calls BLE process events
Hope anyone can help with some ideas or clues! Thanks!!
Show LessThere were rumours about PSoC 7 family. Are we any closer to see the introduction of that family ? On our side, we are in the process of new product development. We would need all that great functionality together with the full 1.8V to 5.5V operation, 24+ UDB and plenty of analogue. Can we expect something like that ? And may be HS USB as well....
Show Less