PSoC™ 6 Forum Discussions

I find the GPIO drive mode settings confusing. If I need a GPIO that is an open drain output with an internal pullup, which do I choose? CYHAL_GPIO_DRIVE_PULLUP or CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW? Something else?

Ok, while I'm here, let me ask these, too:

What does CYHAL_GPIO_DRIVE_PULLUP do? Is the output push-pull or open-drain? I assume that the result would be a push-pull output with in internal pullup, but in what situation would you use that?

What is the difference between CYHAL_GPIO_DRIVE_PULL_NONE and CYHAL_GPIO_DRIVE_STRONG?

Thanks for the help.

typedef enum {
    CYHAL_GPIO_DRIVE_NONE,                /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */
    CYHAL_GPIO_DRIVE_ANALOG,              /**< Analog Hi-Z. Use only for analog purpose */
    CYHAL_GPIO_DRIVE_PULLUP,              /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */
    CYHAL_GPIO_DRIVE_PULLDOWN,            /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */
    CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW,  /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */
    CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */
    CYHAL_GPIO_DRIVE_STRONG,              /**< Strong output. Output only. Output init value(s): 0 or 1 */
    CYHAL_GPIO_DRIVE_PULLUPDOWN,          /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */
    CYHAL_GPIO_DRIVE_PULL_NONE,           /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */
} cyhal_gpio_drive_mode_t;

I have seen the question at cannot program PSOC 6  and my situation seems almost identical but the linked-to thread does not provide the answer.

I have a custom board that has a CYBLE-416045-02 on it plus a 32.768KHz crystal (for the deep sleep timer) and not much else (bypass capacitors, a reset switch and 2 resistive 2:1 voltage dividers to a couple of voltage sources I'm measuring - both have a max voltage of 4v so the voltage seen by the CPU is within range).

The device stopped working a few days ago and when I tried to re-program it I get:

There was an error while programming the device: PSoC Programmer reported error (100 - EraseAll API returned: Error code 0x76FFA400: Unknown SROM status code)

I've tried programming it with a KitProg2 (with the KitProg3 firmware) that was snapped off a CY8CPROTO-063-BLE and is the programmer used to originally program my board, and a KitProg4. I'm using the PSoC Creator V4.3 in Windows 10 64-bit (in a Parallels VM in an iMac running High Sierra 10.13.6) - this is the same environment I used to program the board in the first place.

Can someone please explain what the error code actually means?

Better still, how can it be fixed (step by step instructions please)?

Thanks

Susan

I have a CY8C624ABZI_S2D44 project in full swing but I'm stuck at the complexity of routing GPIOs to the SARDAC. My original notes say that I followed KBA222392 to achieve reading from port 9 GPIOs, but I can't find that app note on the site.

I poll each one of 4 GPIOs on port 9 by routing then one at a time to AMUXBUSA. That has been working for months. Now, I need to add P8.5 to the GPIOs that I am polling. I get readings that say the pin is at ~600mV rather then the voltage I put on the pin. I tried using another spare GPIO on Port 5 and got the same result. Only Port 9 GPIOs are working.

So, what is the difference of using port 9 and port 8? I attached my sample code.

Thanks for any help you can provide.

I’m trying to prototype secure boot using the CY8CPROTO-06204343W PSoC6 dev kit.  A couple of questions:

1. Reviewing the TOC2 format as defined in the Technical Ref manual, the TOC2_FIRST_USER_APP_FORMAT field defines 3 types:  Basic, Cypress Secured, and Simplified Secured.  Where are these formats defined?  I’ve search all of the help and knowledge base articles without any luck.
2. How does the flash boot code know the application size when verifying the image using the RSA pub key?   Is the size part of the application format?

Thanks in advance.

Dean

Hi

I built a project using Arduino Nano (nRF52840 ARM core) which interfaces with a BLE device. The BLE device was shipping with its Arduino Library.

I need to migrate the project to my PSoC, but I do not know where to start from.

I checked the libraries provided by the manufacturer (Veriner GO Direct), and they use the following ArduinoBLE methods:

BLE.available(), BLE.begin(); BLE.connected(), BLE.disconnect(); BLE.scan(); BLE.scanForName();

BLE.stopScan(); BLE.end(); 

My simple experience with BLE led to me hypothesize that if I can find the PSoC-equivalent methods for those mentioned above, I can have a good starting point.

Any thoughts ?

thanks

Hello,
Is there an example code of PSoC6 I2C master using DMA?
My development environment is as follows.

- Modus Toolbox
- CY8CKIT-062-WiFi-BT

Thanks and Regards,
YS

Is it posible to conect ESP8266 ESP-01 WiFi module and psoc6 CY8CKIT 062S2 43012 by use MQTT ?

Dose it have example code ? I have tried the example code of MQTT client by use Modustool box but it didn’t work .

i am not sure if ESP8266 ESP-01 WiFi module can receive the date from Psoc .

Thanks!

Hi all,

I tried a BLE app for bluetooth with Psoc 62S2 Wi-Fi & BT kit. I noticed you must declare mcwdt0 object

cyhal_resource_inst_t mcwdt_0 ={

    .type = CYHAL_RSC_LPTIMER,

    .block_num = 0

};

before the app can compile successfully.

But I prefer to reserve mcwdt0 for CM0+ CPU which is the master control. CM4 is slave which handles radio task.Is it possible to declare and use soft timer such as cyhal_timer_cfg_t timer to do this (or any other timer)? And how can I go about with this?Reason is I want the watch dog to reset the M0 CPU (master)  if it hangs.

Is there a second mcwdt which I can use for this purpose? What will happen if use two separate mcwdt, one each for M0 and M4? Will one mcwdt reset restart the respective CPU only or will it cause both CPU to reset?

Warm regards

CW