Announcements
IMPORTANT: Cypress Developer Community is transitioning on October 20th. To learn more and be prepared for this change, check out our latest announcement.
cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 6 MCU

ChRe_4711096
New Contributor II

Basically - the title. I'd like to know what the delay is between an actual DMA transfer (in my case: halfword-to-halfword) and the corresponding output trigger, if the DMA channel is configured to generate an output trigger.

The background is that I want to copy data to a UDB with a DMA channel, and I'd like to figure out if the UDB can do any sort of processing before the DMA channel's output trigger goes active.

0 Likes
1 Solution
BragadeeshV
Moderator
Moderator

Hi ChRe_4711096​,

The delay between the transfer complete and the assertion of tr_out signal is 1 slow clock cycle (CLK_SLOW).

Regards,

Bragadeesh

Regards,
Bragadeesh

View solution in original post

2 Replies
VenkataD_41
Moderator
Moderator

Hi,

The DMA in PSoC is a dedicated engine works along with CPU. The delay between a DMA transfer and output signal would be very less. So there is no need to worry about this delay. For all the applications you can use the trigger signal output as a point to indicate that DMA is complete.

Thanks

Ganesh

0 Likes
BragadeeshV
Moderator
Moderator

Hi ChRe_4711096​,

The delay between the transfer complete and the assertion of tr_out signal is 1 slow clock cycle (CLK_SLOW).

Regards,

Bragadeesh

Regards,
Bragadeesh

View solution in original post

Top labels