What is the delay - if any - between a DMA transfer and the output trigger?

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ChRe_4711096
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Basically - the title. I'd like to know what the delay is between an actual DMA transfer (in my case: halfword-to-halfword) and the corresponding output trigger, if the DMA channel is configured to generate an output trigger.

The background is that I want to copy data to a UDB with a DMA channel, and I'd like to figure out if the UDB can do any sort of processing before the DMA channel's output trigger goes active.

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BragadeeshV
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Hi ChRe_4711096​,

The delay between the transfer complete and the assertion of tr_out signal is 1 slow clock cycle (CLK_SLOW).

Regards,

Bragadeesh

Regards,
Bragadeesh

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VenkataD_41
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Hi,

The DMA in PSoC is a dedicated engine works along with CPU. The delay between a DMA transfer and output signal would be very less. So there is no need to worry about this delay. For all the applications you can use the trigger signal output as a point to indicate that DMA is complete.

Thanks

Ganesh

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BragadeeshV
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First question asked 1000 replies posted 750 replies posted

Hi ChRe_4711096​,

The delay between the transfer complete and the assertion of tr_out signal is 1 slow clock cycle (CLK_SLOW).

Regards,

Bragadeesh

Regards,
Bragadeesh