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Hello,
We are currently making some radio measurement with our custom board that has a PSoC6 MCU. The hardware engineers would like to get more fine-grained control over the transmission power, than allowed by the 4-bit power code. The technical reference manual states that you can change the interpretation of the BLE_BLELL_*_CH_TX_POWER_LVL registers by changing LL_CONFIG.TX_PA_PWR_LVL_TYPE and instead use and 18-bit value. But how is the 18 bit value interpreted, i.e. what value in the register will correspond to what output power?
Also, is it possible to use the 18-bit value in the real application, or is it only possible when using the Direct Test Mode? If yes, how to you configure this in PSoC Creator?
Thanks in advance,
William
Solved! Go to Solution.
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At final CYBLERD55 design, There are total 12 bits for PA power gain control.
TX_PA_PWR_LVL_TYPE = 0, LL set 4 bits power index to CY55, CY55 decodes internal 6 level look up table which had 12 bits to PA gain. LL set PA gain index via CY55 Reg0x1E02
TX_PA_PWR_LVL_TYPE=1, LL can direct set CY55 12bits PA gain. However there is different register access. (Expecting stack handled this). LL should set CY55 one of Register 0x1065 ~ 0x1060 based on power index set
BTW - from CY55 design view, whether TX_PA_PWR_LVL_TYPE '0' or '1', the final set is to 12bits PA gain. it does not matter either normal mode or DTM mode.
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At final CYBLERD55 design, There are total 12 bits for PA power gain control.
TX_PA_PWR_LVL_TYPE = 0, LL set 4 bits power index to CY55, CY55 decodes internal 6 level look up table which had 12 bits to PA gain. LL set PA gain index via CY55 Reg0x1E02
TX_PA_PWR_LVL_TYPE=1, LL can direct set CY55 12bits PA gain. However there is different register access. (Expecting stack handled this). LL should set CY55 one of Register 0x1065 ~ 0x1060 based on power index set
BTW - from CY55 design view, whether TX_PA_PWR_LVL_TYPE '0' or '1', the final set is to 12bits PA gain. it does not matter either normal mode or DTM mode.