PSoC™ 5, 3 & 1 Forum Discussions

I am planning on taking a course on embedded sensors on Coursera which uses the CY8CKIT-059. However, I am unable to find this kit in stock anywhere online. I was wondering if the CY8CKIT-050 kit could be used instead. I do not have much electrical or development kit background. 

Thanks.

Hi,

I am exercising Bootloader functionality using CY8CKIT-050 PSOC 5LP Dev kit, I have below question on Boatload operation.

I am using single App bootloader (wait for Cmd option is unchecked), and using bootloader Host tool for application upgrade.

Device is flashed with Bootloadable Program 1.

Doing Firmware upgrade using .cyacd file corresponding to Bootloadable Program 2.

Removed Device power (device is powered off) when bootload operation is in-progress, observed that device is running bootloader after device is powered On. This is due to some of the existing application (Program 1) is over written by upgrade program (Program 2), So application checksum validation failed and device is executing bootloader program.

But the question here is why bootload operation is writing the Program 2 in Program 1 space ? If Bootloader didn't write into same space (like written at other space and then overwrite after all bytes get received), at least program 1 will not corrupt and get execute after power On in above power failure scenario.

Do we have any configuration option that can use to avoid this overwrite condition ?

I am attempting to port a project from PSOC5 to PSOC3, using FreeRTOS.   (I started with the SDCC Cygnal port)

This work is being done due to parts shortages.  We need to keep shipping product if we want to stay in business.

Some Cypress parts are 14 months or more before delivery.  (I assume Infineon parts are more important than Cypress parts, at least for now.)  I am trying a stopgap solution if it is possible.   It would be nice to know if the red headed stepchild is going to be buried in the back yard or not, so other designs can be started.

I am still a little fuzzy on the 8051 and the implications of the extensions that Cypress put in place to allow for 24 bit data pointers (DPTR0 and DPTR1).  If this were just assembly, I think I would be ok.

Yes, I know that RTOS for 8051 is a bad idea, etc. etc.  However, the ARM PSOC5 is running around 50mhz and doing fine. The time domain of reporting is flexible and can vary once the data is captured.  The hardware slid into the PSOC 3 quite easily, although I had to give up a SAR monitor that was not really necessary for operation.

In the port.c file, I have come across a compile error for the Keil compiler, and I don't understand what it is telling me.  A google gave no good information, the error # is a generic one for many problems.  The line is as follows:

/* Used during a context switch to point to the next byte in XRAM from/to which
a RAM byte is to be copied. */
static xdata  StackType_t * data pxXRAMStack;

   The StackType_t is uint8.

 The xdata is external data (8 k in this particular PSOC3 processor, 64 k flash).   The data is the internal 256 byte data area.  The comment explains the purpose.

The error is :

ERROR: ..\Source\portable\Keil\psoc3\port.c:61: 'pxXRAMStack': different memory space

How do I handle this error?  I am sure it is some stupid misunderstanding on my part.   The sad thing is it reported to work with the SDCC compiler.    I have read parts of the Keil documentation, an 8051 book, the TRM for the PSOC3, and I am still missing what the error is trying to tell me.

According to the Cx51 User's Guide: Generic Pointers, this is a pointer stored in data that points to xdata.  So why the error?

Should/Could the SDCC compiler be used for PSOC Creator, and allow for debug, etc?  If so, some things might go easier, or might not.

Thanks!

Dear Community,

We are thinking of sending one of the PSOC 5 microcontrollers (CY8C5868LTI-LP039) on our next cubesat-mission.

The chip perfectly matches our needs.  Our question would be if radiation test data already exists or if there is any known use in past space flights. Any sort of information on that matter would help.

Thank you all in advance,

M. N. Schuster

Hello,

I would be interested in understanding how the CySoftwareReset function works, particularly when using a PSoC3: what things are reset? Is the EEPROM memory also reset or deleted? If so, how would it be possible to erase/restore the EEPROM via the firmware?
Thank you all

What is the effective analog BW of the SAR in a PSoC 5LP when using an AMux on the front end? I found someone online claiming 70KHz but I seem to be getting much lower. I'm looking for what it is before it drops 1 or 2 dBV, so a frequency plot would be nice. The specific chip is CY8C5868AXI-LP35.