Anonymous
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Dec 08, 2009
07:02 PM
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Dec 08, 2009
07:02 PM
Hi All,
I'm trying to read from a SAR6 ADC and not getting much joy. I've got the SAR6 input from a PGA, and the PGA clocked at 32kHz.
The PGA and SAR6 are started and set to high power mode. The PGA gain set to 1.
Then a call to SAR6_cGetSample seems to hang at;
mov reg[ASY_CR], ASY_CR_SYNCEN
From what I can gather, this waits for a rising edge on PHI1.
Is it possible that the clock PHI1 isn't running?
Any clues appreciated.
James.
I'm trying to read from a SAR6 ADC and not getting much joy. I've got the SAR6 input from a PGA, and the PGA clocked at 32kHz.
The PGA and SAR6 are started and set to high power mode. The PGA gain set to 1.
Then a call to SAR6_cGetSample seems to hang at;
mov reg[ASY_CR], ASY_CR_SYNCEN
From what I can gather, this waits for a rising edge on PHI1.
Is it possible that the clock PHI1 isn't running?
Any clues appreciated.
James.
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PSoC 1
3 Replies
Dec 08, 2009
08:19 PM
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Dec 08, 2009
08:19 PM
Check if the Analog Power parameter in Global Resources is set to "SC On / Ref xxx". If it is SC Off, then all SC Blocks are powered off and you will not get any result from ADC. Also, check if the column clock to the ADC is within the limits specified in the SAR6 data sheet.
This blog also may be helpful.
PSoC1 ADCs - The Five Golden Rules
This blog also may be helpful.
PSoC1 ADCs - The Five Golden Rules
Anonymous
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Dec 08, 2009
09:42 PM
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Dec 08, 2009
09:42 PM
Yup. SC On / Ref Low.
Maybe the clock I had was too slow. I've now got VC2 at 1MHz as the clock. I find the data sheet a bit confusing in this regard. It says Fclock is Column Clock / 4. So if I choose VC2 at 1MHz, that gives Fclock of 250kHz, which is within the 32 to 333kHz range. Correct?
Now it gets to the next line of code which is initialising SAR6_CR0 - and hangs there 😉
I read through the golden rules. I can't see any problem there.
Any other suggestions?
Cheers,
James.
Maybe the clock I had was too slow. I've now got VC2 at 1MHz as the clock. I find the data sheet a bit confusing in this regard. It says Fclock is Column Clock / 4. So if I choose VC2 at 1MHz, that gives Fclock of 250kHz, which is within the 32 to 333kHz range. Correct?
Now it gets to the next line of code which is initialising SAR6_CR0 - and hangs there 😉
I read through the golden rules. I can't see any problem there.
Any other suggestions?
Cheers,
James.
Dec 08, 2009
10:03 PM
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Dec 08, 2009
10:03 PM
What power do you start the SAR6? The Analog Power should be equal to this power. For example if you start the SAR at Medium power, the analog power should be SC On / Ref Med. Also, the maximum column clock will be different for different power levels for the ADC. Check if this is within limits. Also, check if you have enabled Global interrupts by using M8C_EnableGInt.
You may also want to check out the below example project.
SAR6 Example Project