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PSoC 5, 3 & 1

HuEl_264296
New Contributor II

Hi,

   

 

   

I am trying to set up a PSoC3 to be an SPI master, using DMA to read and write the bytes to/from the peripheral.

   

 

   

However, I also need to insert a small delay of a few clock cycles between the second and thirt bytes transmitted.

   

 

   

How can I insert this delay using the hardware so that the CPU is not involved?

   

 

   

Hugo

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3 Replies
HeLi_263931
Honored Contributor II

Two ideas:

   
        
  • insert a dummy DMA transaction between the two bytes (e.g. copy a memory area into itself or so)
  •     
  • or trigger the DMA externally, using a clock together with a LUT to create the trigger pattern you need
  •    
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HuEl_264296
New Contributor II

 Sadly this won't work. I can't simply interrupt the DMA transfer. If the SPIM's FIFO ever becomes empty, then the SS output will go inactive during that period.

   

 

   

Somehow I need to actually pause the SPIM itself.

   

 

   

Hugo

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HeLi_263931
Honored Contributor II

I see (again 🙂 two options here:

   
        
  • control SS by yourself, not by the SPIM (this is also suggested in the data sheet)
  •     
  • use your own interrupts, and handle the SPI IDLE condition differently
  •    
   

I'm not sure about the second method, since it depends on that SS is handled by the interrupt, and not by the internal state machine.

   

Another option might be to use the byte complete interrupt, and pause/gate the clock supplied to the SPIM after the second byte.

   

Btw: what device do you want to communicate with?

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