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PSoC 5, 3 & 1

Anonymous
Not applicable

Dear sir:

   

     Could many 54LP chips be synchronized by an external clk? If can be, how about its synchronization accuracy? micron sec ? Thank you very much.

   

    Regards

   

    young

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8 Replies
Bob_Marlowe
Expert II

Synchronizing the PSoC's clocks was discussed before, that was not possible.

   

But STARTING the ADCs of several PSoCs can be done by sending out an external SOC-signal that is routed to the ADCs.

   

Since (as always a good practice) this signal is synchronized to the internal clock you may be off for one to two clock cycles which is when running at 60MHz something like 30ns. The point from where the ADC actually starts may depend on a pre-divider (I am not quite fit with the ADC internals) but that will not be more than factor 4. So you can be quite sure to start your ADCs within the same microsecond.

   

If this is not sufficent, create a so-called "MyCase": At top of this page -> Support&Community->Technical Support ->Create a MyCase.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

Can  you describe in a little more detail why clocks synch is

   

needed, eg. where design constraint comes from ? What you

   

are trying to accomplish ? And what performance you need,

   

jitter, phase shift allowed, etc..

   

 

   

Regards, Dana.

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HeLi_263931
Honored Contributor II

Since the PSoC5LP can be clocked by an external (main) clock, they can run in sync. But you still need to ensure that they start at the same time - for that you need a separate synchronization signal.

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Anonymous
Not applicable

HI,expert::

   

    The ADCs of many PSOC5 (if I finally choose the chip as the controller) need to be synchronized, and the sample frequency will be about 1-4 KHz. The external strobe signal will trigger the conversion of ADC. I need to know if the CY8C54LP could fulfill the task.

   

    Thank you very much.

   

    Regards.

   

    Young

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Bob_Marlowe
Expert II

Starting a couple of PSoC5's ADCs at the same time can easily be done using an external pin connected to the SOC input of the ADCs. The ADC clock could be distributed from external, too. Additionally the pin's input could be synchronized to another (external) signal so you have several different options.

   

BTW: Why don't you use a CY8C56 -LP PSoC which contains two (2) SAR-ADCs instead of only one as your selected CY8C54-LP chip? Both SARs can run independently and might be started with the same signal using SOC input and ADC clock.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

You might file a CASE to check me on this, but I believe the SAR has

   

a fixed sampling time front end vs the DelSig. So if you are trying to sample

   

several signals at precisely the same time SAR would be component

   

of choice. Or use separate S/H and synch them so that you can use

   

DelSig. Thats the Sampe Track and Hold component in Creator.

   

 

   

Note of course you have to consider noise and droop/accuracy tradeoffs

   

of the S/H approach.

   

 

   

Regards, Dana.

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Bob_Marlowe
Expert II

The CY8C54-LP family doesn't contain a DelSig ADC

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

But some members of the 56 family do.

   

 

Regards, Dana.   
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