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PSoC 5, 3 & 1

DeMA_2593386
New Contributor

How to insert a 16bit data from MainC into  the schematic Design 16bit Bus

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1 Solution
odissey1
Honored Contributor II

DeMA,

Usually to make  a 16-bit bus one has to use  two Control Registers, 8-bit wide each, and combine their outputs into a single 16-bit bus. Then in C code, the MSB of the 16-bit value is assigned to one CReg (bits 8-15), and LSB to another CReg (bits 0-7). Note that such operation is not atomic, but sufficient in most cases.

To simplify this, I created custom ControlReg32 component, which has bus width up to 32-bit. You can find demo project here:

[Verilog] Register access using CY_SET_REG

In the basic dialog set the CReg width property to 16.   Then in mein code use API:

CReg_Write(value);

/odissey1

Reg32_01c.png

View solution in original post

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1 Reply
odissey1
Honored Contributor II

DeMA,

Usually to make  a 16-bit bus one has to use  two Control Registers, 8-bit wide each, and combine their outputs into a single 16-bit bus. Then in C code, the MSB of the 16-bit value is assigned to one CReg (bits 8-15), and LSB to another CReg (bits 0-7). Note that such operation is not atomic, but sufficient in most cases.

To simplify this, I created custom ControlReg32 component, which has bus width up to 32-bit. You can find demo project here:

[Verilog] Register access using CY_SET_REG

In the basic dialog set the CReg width property to 16.   Then in mein code use API:

CReg_Write(value);

/odissey1

Reg32_01c.png

View solution in original post

0 Likes