Announcements
IMPORTANT: Cypress Developer Community currently doesn’t allow sign-in to prepare for the upcoming transition. To learn more, check out our announcement.
cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1

Anonymous
Not applicable

I am trying to implement a comparative analysis of subjected control methods for my bi-directional dc-dc converter. I came to know about opamp implementation through an example from document AN76439(related image is attached).
But, there are two other methods to complete the same task without using op-amps i.e. FPGA and DSP(TMS320C200 by TI). I want to implement both of these methods on PSoC independently in order to check their performance.
So, my question is that, is there any project or doc related to implementation of  feedback-compensation control method using MCU(ARM-Cortex) and using UDB's or Verilog. 

0 Likes
6 Replies
odissey1
Honored Contributor II

muhammad, PSoC5 and TMS320C200 are in different weight categories, and  PSoC5 does not have real FPGA. I believe that about 100kHz feedback loop is possible with PSoC5, but have not seen any implementation so far.

0 Likes
Anonymous
Not applicable

Well, the loop is 20kHz. I got few online tutorials not related to PSoC but generally applicable to FPGA and MCU's (see the link below) implementation. I will try to implement it. I do have a question according to algorithm mentioned in link below. According to your experience with PSoC, will there be any chances of performance difference between two implementations? One will be in C code by utilizing PSoC 5LP's MCU and other with Verilog utilizing UDB's. Thanks in advance, waiting for your kind reply. 

http://www.controlsystemslab.com/doc/b4/pid.pdf    

0 Likes
odissey1
Honored Contributor II
        mohammad, I thought you need 150-300kHz loop for DC-DC converter. 20 kHz loop will work using PSoC5 CPU even using floating point math. In the reference you provided it takes 3 multiplications for loop cycle; each float multiply eats approx. 100 CPU cycles, so total ~300 tics plus servicing ADC, etc. will bring it to 500-1000 tics, which is 24kHz on 24 MHz CPU. So that is no problem. You will get even faster loop using fixed-point math. The PID algorithm is a part of the DSP library provided in ARM CMSIS-DSP http://www.cypress.com/forum/psoc-creator-software/including-cmsis-library-psoc-project Now about Verilog implementation. PSoC Verilog will max out resources at about one 8-bit multiply, so there is no room to program it in Verilog as-is. UDB does not have multiply function either. I suggest to open and inspect Cypress Fan Control component, which allegedly has PID implemented in UDB (I was unsuccessful with decoding it - component implementation is too big).   
0 Likes
Anonymous
Not applicable

Thanks for such a well articulated response.
The library you mentioned will help me to perform floating point math while implementing PID?

0 Likes
odissey1
Honored Contributor II

CMSIS library has both float and fixed math (Q-numbers) implemented, so you can find right balance between accuracy and speed.

   

link to CMSIS

   

http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.p...

   

 

   

 

   

 

   

Also your 'dsplib' article gives a generic PID algorithm, to read more about PID control algorithm implementation in FPGA look at this article (up to 11 MHz loop speed):

   

http://www.embedded.com/design/configurable-systems/4212241/Case-Study-of-PID-Control-in-an-FPGA-

0 Likes
Anonymous
Not applicable

Stay Blessed 🙂

0 Likes