My overall goal is to sample two signals at 30 ksps / signal (60 ksps total) and send the data via a wireless protocol such as bluetooth.
I'm able to sample one signal at 10 ksps using a 8-bit delta sig ADC. I'm able to send a few seconds of data at 10 ksps to the pc via UART. I may need to configure an external clock to get the required baud rate to match my hardware for 30 ksps.
My code currently sends one byte after each ADC conversion. I don't think that this is the best way, and I'm afraid it won't work well for 30-60 ksps.
As usual the answere is : That depends...
If you are continously sending your data via an UART check first if all the bits can pass.
Let us estimate: 60 ksmp/s times 12 (for the overhead like stop-bits etc) that is 720kbaud. That's a lot and I question if that would be possible.
If you are not continously generate data, there is an upper limit for yout data, for instance 250 data-points. In this case I would suggest to use a software- technique (circular Buffer) to store the data and to send them out concurrently.
Hope that helps. Have fun
I will most likely only need to capture 500 ms of data every 1-2 seconds. That means I'll have 500-1500 ms extra to send the data.
How big of a circular buffer should I try?
Some comments on your source:
It is always advisable to post the complete project (in the right forum) using Designer "File -> Archive Project..."
You do not check your Rx for a character beeing ready.
After switching the AMUX the next 3 ADC-values should be discarted.
There is no buffer I can see that may overrun.
There is an example project using USBFS, described as follows -
This project enumerates USBFS component as a 8-bits, 32kHz, mono USB Audio Device. The audio data is passed to 8-bit DAC using two DMAs. One DMA is integrated in USBFS component used for sending and receiving data to/ from the memory cyclic buffer; the other DMA (VDACoutDMA) moves data from memory buffer to VDAC8.
The synchronization of incoming transfers with internal 32kHz clock is done by the software. It works when cyclic buffer overflows.
When internal 32kHz clock is faster compared to PC transactions, VDACoutDMA stops for a while to fill the buffer.
When internal 32kHz clock is slower compared to PC transactions, then one USB transfer is skipped.
This project doesn't work with PSoC5 silicon due to the use of DMA Endpoint Memory Management in the USBFS component.
You might consider working with this and modifying the example.
@jataalfer: please don't hijack old threads with new questions - please open a new thread. This will increase you chance of getting a good answer.
Also, note that this is the PSoC3 forum. If you post to a PSoC1 forum, you are also more likely to get a good answer (not all PSoC1 gurus read here...).