PSoC™ 5, 3 & 1 Forum Discussions

i need to create 6 signal that drive a three phase bridge  with a frequency =3600hz

i can do it by timer and a switch case like :

but when i use serial to contact with pc and send a frame , the interrupt to timer wait until the frame is send , so the frequency is not fixed.

how to implement it without using CPU to change the port case . like PWM that working without CPU assistance؟

I have a FreeSoc2 development board with the 5888 part, MASTER_CLOCK comes from an external 24MHz crystal and is bumped up to 64MHz by the PLL. BUS_CLK==MASTER_CLK. Release build with LTO etc. enabled, optimization goal set to speed. Debugging a soft 3-wire SPI implementation I ended up with the following snippet:

    for(;;) {
    
        Soft_SCLK_DR |= (1 << Soft_SCLK_SHIFT);
        Soft_SCLK_DR &= ~(1 << Soft_SCLK_SHIFT);
    }

The output frequency on the Soft_SCLK pin is 4MHz -- I expected it to be in the 15-20MHz ballpark. So why is it so slow?

Hello All,

I have a design using an SPI slave (PSoC 3/5) with the following parameters:

    
• CPHA=0, CPOL=1
    
• MSB First
    
• No data being received (MOSI is zero constant)
    
• 8-bits wide
    
• 4 Byte FIFO
    
• External Clock (24 MHz BUS_CLK)
   

The application requires that, while SCLK is in its idle state, MISO be a steady high to indicate that the device is ready for a data transfer.  Immediately after the last SCLK, the MISO must go low to indicate that the device is not yet ready for another transfer.  Once the device is ready, the MISO will go high.  I can add logic to the SPIS to force these conditions, but before I do that, I think I should better understand the SPI slave.

I will only transfer 4 bytes at a time.  And, since the clock is much faster than SCLK, I consider a delay of a few clock cycles to be essentially instantaneous.  I don't want to use the SS input, but if I have to, I'll use internal signals to "fake it out".  That being said, I want to determine/control the MISO state before and after the transfer.

Assume that the FIFO is full and I have written directly to the shift register using SPIS_WriteTxData() before the first leading (falling) SCLK edge.  What is the MISO state?  Is it equal to the MSb of the first byte, already in the shift register?

Also, what would the MISO state be after the trailing (rising) edge of SCLK?  Would it be the LSb of the final byte, the MSb of the next byte from the FIFO, or something else?

Any help would be appreciated.

Paul

Hi,
We are trying to acheive something like Sigma-Delta ADC -> DMA -> Filter_Block -> DMA -> SRAM. Initially we started testing
with ADC -> DMA -> Filter_Block-> Interrupt. The readings obtained were as expected. However when we tried replacing the 
interrupt with DMA {Sigma-Delta ADC -> DMA -> Filter_Block -> DMA -> SRAM} we noticed the readings not as expected. 
For the 50 tap filter the readings kept changing till the 49th sample and then it remained constant. 
I have attached the project bundle. Kindly help me figure out the issue ?

Thanks

I'd like to make DMA transfer 2 data from SAR ADC to Memory as switching AmuxHW, but the output of DAC was mixed signal of 2 data (reference to attached picture:Blue= SIG1, Yellow=SIG2, Green=output of DAC). 

Digital delay circuit was referenced to CE95299 (http://www.cypress.com/documentation/code-examples/ce95299-delta-sigma-adc-using-16-multiplexed-single-ended-inputs-psoc). 

Hello,

assume F0 is in dynamic, edge triggered mode and is controlled by UDB, (stores from A0). It contains [1, 2, 3, 4], A0=5. Now, let there be a datapath sequence of states

PASS A0, (A0 WR SRC = F0)

ADD A0, A0

and the FIFO write strobe generates a rising edge when control goes to the ADD. There are two possible scenarios in that state:

a) F0 = [2, 3, 4, 5], A0 = 1 (read and write were merged: I'd like this to happen)

or:

b) F0 = [2, 3, 4], A0 = 1 (because: A0 is first written to a full FIFO, so ignored, then the FIFO is read into A0)

or:

c) undefined.

Which one will happen? I can check it on a real device, but I don't consider it a proof of anything -- is there a documentation backup for that behavior?

    Best regards,