PSoC™ 5, 3 & 1 Forum Discussions

hi, there

   I am using CY8C29466 as the mcu of a mems sensor.  I need to get the output from the e2prom according to the analog input, which is as used an index to search the data in e2prom. Before this , the calibrated data more than 1000 in a text file is needed to write into the e2prom first. But I don't konw how to do this?

   I have researched the related file to e2prom, AN2015. It uses an an array to store the data written into the e2prom. However, this is not practical when there is a lot of data to be written.

   Does  anyone konw any other method to download the calibrated data into e2prom?

Looking forward to your reply!

LU

Hi,

I'm having a difficult time with changing my PSoC's CPU clock (bus clock) to 72MHz.

I followed the instructions, but I still get this error: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK ).

I attached few screenshots so you can understand more easily the problem.

P.S.

I won't be able to upload the project.

Hi all,

as said on title, is there a way to put custom written firmware on detachable Kitprog board of CY8CKIT-059?

Thank you,

Simone

Hi,

I am using the CY8CKIT-059 prototyping kit with the KitProg onboard programmer and debugger.

For testing and development purposes it is important to have an insulation between programmer and target.

To break the two boards apart is easy but to find a suitable digital isolator is tricky.

The SWD clock is running at 4.5 MHz and that is too fast for the most isolators.

Is there a possibility to reduce the programming/debug clock speed of the KitProg?

Hi,

I'm trying to create a CRC16 (poly 0x1021, initial value 0x0000), and ideally I would like the UDB's to do the serial input XOR (i.e. not using the EXTCRC function).

I'm simulating to confirm the device using the cy_psoc3_dp.v model in the warp sim library and despite having looked at how I should configure and connect the UDB's, I can't get any sensible operation from the simulation.

So firstly I observe that the CRC_v2_40 module in the library uses EXTCRC calculations for the feedback, and I can't find an example that uses the internal feedback, which makes me concerned that there might be an issue with the internal feedback.

Also when I look at the simulation model, cfbo from the least significant byte comes from sir ^ msbo, but I need to feed in the external serial in, into route_si. PSoCCreator will not allow me to feed it into sir (it only expects chaining signals).

I would have expected that in the cfbo equation that sir would be replaced by an s_r_source.

I am using ISSP programming on a cy8c27143 with an atmel 2560. I am having trouble getting the verifying ID chip to work. I am using serial an I receive a 0x00 and 0x08. I should be receiving a 0x00 and 0x09. Am I anywhere close to getting it right and I'm just making a simple mistake? should I stop with just using serial and implement a bit bang to achieve a proper High Z state? Was there a change in cypress IDs in the past? Could I just skip the verification ID and go on to the next steps in ISSP programming? Any information wold be helpful

Some time, when i  change components in 'topdesign' and click 'build design'

All of my code is erased under "/*  Place your Interrupt code here. */" in psoc code

how can i maintain my code under "/*  Place your Interrupt code here. */" in psoc code after changing component?