PSoC™ 5, 3 & 1 Forum Discussions

Hi,

I have a few questions regarding IDACs in PSoC 5LP CY8CKIT-059:

1. In datasheet it's stated that the maximum DAC sample rate is 8 MSps and that the settling time to 0.5 LSB is 125 ns for 255 μA range for full scale transition, DACs running in fast mode and using 600 Ω 15-pF load.
   • What happens if I strobe the DAC with frequency higher than 8 MHz? I assume that the DAC will work fine, but it won't be guaranteed that the output will settle to 0.5 LSB until DAC is strobed again. Is settling time for something like half scale transition lower than for full scale transition and is it affected by the load attached?
2. How are DACs trimmed? I'm using 4 IDACs  in source mode and would like to get the as close to ideal as possible, but it's even more important to get them as close to each other as possible.
   • I found this question already answered in this thread, but it did not work for me:

A sample Calibration routine does the following: The goal is to adjust the calibration code to get 256uA from the IDAC when the input code is 255 in the mid-range: Fix the digital input code to 255 and the calibration code to 128 (128 = 0b10000000 is the default value) and capture the DAC output. Determine the gain error. Apply the correct calibration code and capture the DAC output. The default value of the Cal[7:0]  is [10000000]. Values lower than this will decrease the gain and values greater than this will increase it.

• When I increase the calibration code (for example 10000111) output current is decreased, but if I understood this correctly it should actually increase.

               What am I doing wrong and what would be the best way to trim all 4 DACs to get them as close to each other as possible?

               Is there any specific way that this measurement should be done? I tried connecting an ammeter directly between DAC output pins and ground and also through a 1k and 3.7k resistors, but it always behaves the same way.

               This is an example of how I'm trimming the DACs in code:

IDAC_0_trim_val = 0b10000111;
CY_SET_REG8(IDAC8_0_TR_PTR, IDAC_0_trim_val);

     3. I've found a DAC Block Test Register in PSoc5LP_Registers_TRM, but I can't find any application notes or discussions about it. How does it work and how and when should it be used?

Any help would be appreciated.

Hello,

I have two circuit boards interconnected by a cable that communicate using I2C. The JCK-1 board contains the I2C master. THe PSU-1 board contains the slave. The code as it is written now is able to write information successfully to the slave.

However, I am having trouble getting the master to read back information from the slave. The master, after sending out the read request, just sits in the read status loop and hangs. I set up an array of 4 numbers as test information to keep things simple.

Please assist in troubleshooting my code. The issue probably is simple.

Best Regards,

Ben

I work with the PSoC 5LP Prototyping Kit, and I try to connect with the I2C to the MPR-121 component and read the values from it. Can I get some help on this? Can't figure out which register I'm supposed to send the commands to, and how it should be executed exactly.

Thanks

What will be the best interface option for exchanging bi directional  data stream between two PSoC3 boards.

Regards

Hi all,

I have been working UART communication via radio between PSoCs. I want to be able to detect errors during communication for which I have been recommended to use some sort of checksum. Below is the scheme I am using to send the data.

Start Byte, Byte 1, Byte 2, ....., Byte N, chksum, CR

Now, I just want to understand how the cheksum would work. I understand that the receiver would also send the calculated cheksum back and should they match, I would have no error, and if they don't I would have an error.

The one thing I don't understand is how would the transmitter know if there was an error. Does the receiver send an acknowledge signal? How does the receiver know which byte is the cheksum byte? What if the cheksum did match and the receiver sent back an ack signal, however the message got lost along the way signifying an error eventhough there was not one?

Hello,

i am new to the world of PSOC and have more of a digital, than analog background, so i hope my question is somewhat valid.

I'm doing a project and try to build a signal simulator for it - very weak signals. I use the CY8CKIT-059 kit. For basic testing i use this setup:

The WaveDAC is an iSource. The VDAC is there to pull the signal to zero, so i can lower the input range of the ADC. The digital filter in the end is there so i can calculate the signal to noise ratio (SNR). In this setup i get a sinus signal between about 0 - 2.2V.

My goal is to dampen the signal. just in this setup i have two possibilities to do so

a) lower the WaveDAC output range to either 0-255 uA (8x smaller) or 0-32uA (64x smaller)

b) make the resistor smaller

a) works perfectly. the ADC reads signals that are about as much smaller as they should be. if I test with an oscilloscope at the Testpoint (TP) it's somewhat the same.

b) on the other hand does not at all, what it should (or at least i think it should).
if i replace the 1K Resistor at R_DAC with a 10 Ohm resistor, the signal should be 100x smaller (0-20mV). if i test with the oscilloscope at the TP it is roughly in the correct neighborhood. the signal has a 20mV offset and is only 66x smaller, but that is still much closer, than what the ADC reads. Peak-to-Peak the ADC gets 220mV, so only 10x smaller instead of 100x.

if I use a 1 Ohm resistor, it should be 1000x smaller (0-2mV). The oscilloscope tells me of 8mV peak-to-peak (275x smaller), but the ADC reads 175mV peak-to-peak (only 12x smaller!!)

What do i do wrong? The ADC is set to continous and bypass buffer, so there should be no gain, or?

The signals look fine - i get an SNR of mostly over 50db.

I plan on trying out current dividers and opamps to dampen the signal, but would rather like to keep it as simple as possible.

To whom it may concern,

Would it be possible to provide more details regarding the following excerpt:

- What is the minimum resistor value that can be used as a ‘strong’ pull-up on the MSB?
      -> Can it be shorted to either VDD or VSS?
      -> Equally what happens if resistor to VDD/VSS is >200k or left open?

- How do the address pins sense the strong pull-up?

- How tolerant is this sense circuitry tolerant to noise?
      -> Are decoupling capacitors required?

- What will happen if a resistor value between 330~75KOhms is tied to the address pins?

- Are the 330 Ohms and 75kOhms defined to work over the -40 ~ +85C temperature range?

- Are the Address bits pull up/down resistors only sampled once at power-up?
      -> Are there any timings/thresholds for which pull state must comply to?

Look forward to hearing from you.

Many Thanks,
Bhav