PSoC™ 5, 3 & 1 Forum Discussions

Hi all,

I am working on an RC car project and for this project I am using a multitude of sensors (speed, GPS, Proximity). So far, I've been running through a single while(1) loop, however, I've been thinking about exploring the possibility of using FreeRTOS to manage all the sensors in the system. (I have no experience using RTOS but I would like to start somewhere)

Now, this uses radio communication over UART in order to receive the commands for the car's movement.

My question is: Would you recommend using an RTOS for something like this?

Hi,

In my board design I have connected these 2 analog pair inputs to the SIO pins in the PSoC:

AIN_O6P = P12_2

AIN_O6M = P12_3

*M refers to GND path which belong to this specific analog input.

*P refers to the analog input.

Please your support understanding how to configure these SIO inputs.

Thanks,

Roy Roif

Hello,

I have a question about the USBFS component and API as it pertains to managing connection/disconnection from a USB host.

The system I am working with is self-powered.  VBUS is a little weird in this design.  The PSoC does not have any access to VBUS directly.  the signal I am using in place of VBUS Detect is a signal that is high when the PSoC is selected by a USB 2.0 mux.  When the other USB device on the mux is finished, it switches the mux over to the PSoC5LP and alerts the PSoC that it has been selected.  So basically, VBUS Detect is high when it's *possible* for a host to be connected, but most of the time there is no actual host on the other end (the connection is mostly just for bootloading).  See below:

One thought I had was to use USBFS_GetConfigurationChanged() to detect the config change when a host connects, but what I'm finding is that even without a host connected, it will still pass through if(USBFS_GetConfigurationChanged() != 0) immediately, without regard for if a host is actually connected.

Is there a way through software to detect a connection event without having VBUS available as a trigger?

Thanks for the help!

Dear Sirs and Madams,

We are considering the low power mode of PSoC5LP.

Hibernate mode ⇔ active

Sleep mode ⇔ active

PSoC5LP repeats the above state transitions.

When the master clock of PSoC5LP is set to 68MHz (using PLL),

The operation is always stuck by the return CyPmRestoreClocks () ;.

The reproducibility of this problem is 100%.

/******** Software excerpt ********/

CyDelayUs(20);

CyPmSaveClocks();

CyPmHibernate();

CyPmRestoreClocks(); // <= Stack in this process

CyDelayUs(20);

However, when the master clock is set to 24MHz (using PLL),

This stacking problem does not occur at all.

Is Cypress aware of this issue?

Do you have a countermeasure plan?

Regards,

I would like to replace the UART Bootloader Host Application executable with a program written in LabVIEW. 

Ideally LabVIEW would call a dll like BootLoad_Utils.dll that has a function Bootload. 

The Bootload function would take in parameters: COM Port, Baud Rate, and Bootloadable File and it would output the Status Log. 

Alternatively there could be functions like Set_COM_Port, Set_Baud_Rate, Set_Bootloadable_File, and Start_Bootload. 

It would also work if functions like these can be sent from the command line. 

Do these libraries and functions exist?  Is there documentation for how to use them? 

Thanks

I have executed the following function to initialize the I2C slave device, but it seems that communication is not working properly.

I2CMAST_MasterClearStatus();

Stat = I2CMAST_MasterWriteBuf(AQM0802_ADW, &TestData, 2,  I2CMAST_MODE_COMPLETE_XFER);

for(;;) {

     if(0u != (I2CMAST_MasterStatus() & I2CMAST_MSTAT_WR_CMPLT))

break;

}

※Note　Slave Address:0x7c、The contents of TestData are 0x80,0x34

Additional information：Implementation is a fixed function

The actual waveform as a result of executing the WriteBuf function is　（See attached document)

It seems that only the first slave address is transferred from the actual waveform

There seems to be no problem with the transfer timing of the slave address．

I would appreciate any good advice on this phenomenon.

Thank you

Dear Sirs and Madams,

We would like to know errata information about PSoC Creator and PSoC5LP(Includes all components).

I checked the website but couldn't find it.

Is errata information about PSoC posted on the Cypress website?

Regards,

Hi,

I dont know why, but the Delta Sigma ADC [ADC_DelSig] component is missing in my PSoC Creator when I am trying to design a project for my PSoC Chip [CY8C5467AXI-LP108], yet it is shown for my other PSoC Chip [CY8C5868AXI-LP035].

I dont understand why it is happening since it is written in the datasheet that the CY8C5467AXI-LP108 PSoC Chip also has delta sigma adc in it.

Please your support according to these information:

PSoC Chip - CY8C5467AXI-LP108.

PSoC DVK - CY8CKIT-001.

PSoC Creator - Ver 4.3

Thanks,

Roy Roif.