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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

Your discussion "PSoC Today! - Synchronous Detection Part xx" sort of nails what I want to do with a fluxgate magnetometer project (similar to LVDT transducer application) but I find the video a bit glib, and would really like a resource that guides me through the modifications to the ADC etc to produce the working project.

Are the design files available to help me create  a working prototype ?

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1 Solution
odissey1
Honored Contributor II

Attached is a demo of Lock-in detector which can operate in 100Hz - 10kHz range. It utilizes built-in modulator stage of PSoC5 DelSig_ADC. The Device Under Test is a simple bridge with a trimpot, producing differential output in the range 0-1V. The demo shows three ways of filtering ADC data stream: (1) directly filtering ADC data using first-order IIR filter and ADC interrupt; (2) using DMA to transfer ADC data to digital Filter (and polling Filter output); (3) further decimating data from Filter output (on interrupt) and passing it through another IIR filter. All three results are displayed using plotting software (Multichart) at 100 samples/sec, allowing to compare results.

Project utilizes several custom components: DDS24 (tunable freq. and phase generation), QuadDecoder_SW (for interfacing to a rotary shaft encoder to change frequency and phase), CY8KIT-059 off-chip annotation library. They must be loaded into Project->Dependencies. Use links below to download them:

DDS24: 24-bit DDS arbitrary frequency generator component

Quad Decoder with Button Switch component for rotary shaft encoders

Annotation library for CY8CKIT-059 Prototyping Kit

Attached below are project file, Multichart GUI, and screenshots demonstrating noise level for 200mV p-p input signal, and response time for 0-200mV ramp. Note that most noise originates from USB power fluctuations on (digital) driving pins.

odissey1

DelSog_lock-in_06_sch.png

View solution in original post

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10 Replies
odissey1
Honored Contributor II

What is the modulation frequency you need?

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Anonymous
Not applicable

10kHz max, probably in 2-5kHz range. Somewhat undefined until we sort the magnetics

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odissey1
Honored Contributor II

Attached is a demo of Lock-in detector which can operate in 100Hz - 10kHz range. It utilizes built-in modulator stage of PSoC5 DelSig_ADC. The Device Under Test is a simple bridge with a trimpot, producing differential output in the range 0-1V. The demo shows three ways of filtering ADC data stream: (1) directly filtering ADC data using first-order IIR filter and ADC interrupt; (2) using DMA to transfer ADC data to digital Filter (and polling Filter output); (3) further decimating data from Filter output (on interrupt) and passing it through another IIR filter. All three results are displayed using plotting software (Multichart) at 100 samples/sec, allowing to compare results.

Project utilizes several custom components: DDS24 (tunable freq. and phase generation), QuadDecoder_SW (for interfacing to a rotary shaft encoder to change frequency and phase), CY8KIT-059 off-chip annotation library. They must be loaded into Project->Dependencies. Use links below to download them:

DDS24: 24-bit DDS arbitrary frequency generator component

Quad Decoder with Button Switch component for rotary shaft encoders

Annotation library for CY8CKIT-059 Prototyping Kit

Attached below are project file, Multichart GUI, and screenshots demonstrating noise level for 200mV p-p input signal, and response time for 0-200mV ramp. Note that most noise originates from USB power fluctuations on (digital) driving pins.

odissey1

DelSog_lock-in_06_sch.png

View solution in original post

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Anonymous
Not applicable

Wow - amazingly complete. Thankyou very much. Looks like some very useful tools in there as well.

Appreciate your effort!

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odissey1
Honored Contributor II

It would be interesting to see a progress you make with magnetometer project. Please share your experience if permitted.

The demo provided is a bare basic lock-in design in one of many incarnations possible with PSoC. It all depends on frequency of operation, input signal/noise, time constant and necessity to measure quadrature signals.

More targeted design can be provided if you can share those specs.

odissey1

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Anonymous
Not applicable

Odissey1,

I am newbie in PSOC so please excuse if my question does not total sense.

I gather from the above discussion that your SD requires PSOC3 & PSOC5 platforms. with a built-in ΔΣ-ADC. Can this SD be implemented within any PSOC4-BLE modules by any chance? This would make an excellent compact sensor reader with BLE connectivity but I see that PSOC4 has only SAR-ADC unless there is a creative way to re-purpose capsense ΔΣ-ADC?

BTW, we have been using PSOC 5LP Prototyping Kit with an external dongle, which is not small enough in our application for optical reading.

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odissey1
Honored Contributor II

I can't comment about PSoC4 BLE use for lock-in detection right away due.to it's limited hardware resources. I will look into it. What frequency range is if interest for you application?

odissey1

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Anonymous
Not applicable

1-10kHz would be fine for frequency

Could the CY5677 CySmart BLE 4.2 USB Dongle work? It has a PSOC5 onboard and I wonder if it can be repurposed. It does not provide any GPIO pins though...

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odissey1
Honored Contributor II

@ user_460324383,

PSoC BLE has 4 OpAmps, Analog Mux (with HW control) and SAR_ADC (with optional averaging up to 256 samples). Within those resources I see three possibilities:

1). Using one OpAmp as modulator (+/-1), followed by second OpAmp configured as Sallen-Key LPF with cut-off frequency ~100Hz. SAR_ADC used to digitize DC output with secondary averaging using built-in aggregator (up to 256). This is proven standard approach, which requires handful of-chip resistors and couple of capacitors.

2). Hardware-controlled Analog Mux can be used as modulator, followed by SAR_ADC as LPF. The drawback is lower dynamic range, compared to (1), because averaging is performed in 12-bit space.

(3) Input signal directly digitized by SAR_ADC and On-Off difference obtained in post-processing. The dynamic range will be even lower than in (2), because On-Off difference will have less than 12-bits available.

A while ago I tried (1) and (3) to some success using PSoC5 (at that time Del-Sig ADC had no modulator input). With PSoC BLE I would go with (1), as it is standard approach.

odissey1

PS

(1) the link exemplifying modulator OpAmp

https://www.eetimes.com/document.asp?doc_id=1225656

Synchronous demodulator | Gas station without pumps

and

(2) analog Mux utilization for lock-in detection

Optimizing Precision Photodiode Sensor Circuit Design | Analog Devices

Analog Devices_Photodiode Lock-in_figure10.jpg

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Anonymous
Not applicable

Thanks a lot for the detailed answer and all the help. Makes sense. I will implement (1) and get back to you.

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