Need help in IIR Filter design in PSOC 5LP?

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Anonymous
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Hello Everybody,

   

I am programming an IIR Filter and following the cypress application note AN2099 (PSoC® 1, PSoC 3, PSoC 4, and PSoC 5LP - Single-Pole Infinite Impulse Response (IIR) Filters).

   

I dont know how efficient it would be. Can any body guide me regarding this?

   

My Specs are:  My cut off frequency is 2Khz.

   

and sampling frequency is 24KSPS.

   

My attenuation factor would be i think 1.9 so i selected 134/256 (based on the formula given and recomendation).

   

Looking forward for your reply.

   

 

   

Best Regards

   

Awais

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1 Solution
Bob_Marlowe
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As stated in the document, the attenuation factor does not need to be done using shifts and adds when using a PSoC5. There is a fast multiplier within the M3 CPU that will reduce execution time.

   

The programming of a project like yours is done easily, so best will be to start and confirm for yourself "how efficient it would be".

   

Whatever your criteria for efficiency are.

   

At 24ksps CPU time gets tight, so running the PSoC at highest frequency and setting compile options to "Speed" will be needed.

   

 

   

Bob

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Bob_Marlowe
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As stated in the document, the attenuation factor does not need to be done using shifts and adds when using a PSoC5. There is a fast multiplier within the M3 CPU that will reduce execution time.

   

The programming of a project like yours is done easily, so best will be to start and confirm for yourself "how efficient it would be".

   

Whatever your criteria for efficiency are.

   

At 24ksps CPU time gets tight, so running the PSoC at highest frequency and setting compile options to "Speed" will be needed.

   

 

   

Bob

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Anonymous
Not applicable

Thank you Bob for your reply.

   

"so running the PSoC at highest frequency and setting compile options to "Speed" will be needed." How i can make these settings?

   

Also one more thing!

   

The given program is for i think single order filter. How i can make it for greater then 1st order?

   

Looking forward for your reply.

   

 

   

Regards

   

Awais

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Bob_Marlowe
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Clock is changed in .cydwr view (where the pins are selected) using "Clocks"tab and double clicking on a clock entry.

   

Compiler options are to be found in Project->Build Settings->Compiler->Optimization.

   

Yes, the example is a first order filter. Don't know the math for second or more order filters.

   

What is the reason you do not use the filter component within the PSoC5?

   

 

   

Bob

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Anonymous
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The reason is, i already used that filter block (both channels). But i also need another block of filter which i dont have 😞

   

Awais

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Bob_Marlowe
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That might get really tough! The two channels will use some CPU power which you would need for your filter.

   

 

   

Bob

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Anonymous
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Thankyou Bob for your reply.

   

I didn't get it completely. Can you please elaborate it? How i can know all these issues?

   

Looking forward for your reply.

   

Best Regards

   

Awais

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Bob_Marlowe
Level 10
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Your sampling rate is 24ks/s which leaves 1000 machine cycles @24MHz including the cycles needed for interrupt handling, calculating the filter etc. That is not much. Since we cannot overlook your complete project we cannot tell if it fits or not. You did not tell where the filtered data go to and whether there is CPU power needed for that. I would suggest to start designing and see what fits and what not.

   

 

   

Bob

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