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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

Hello All,

   

Has anyone been able to successfully measure the Max voltage of a sine wave?

   

I am routing my analog wave through a PGA before inputting into the ADCINCVR. The Clock frequency is set to 2Mhz, the CPU is set to 12Mhz. The input wave is 3Vpp @ 3840Hz with a DC bias of 1V.

   

    while(1){
        if(ADCINCVR_1_fIsDataAvailable()){                // check flag to see if last conversion is complete
            ADCcount[0] = ADCINCVR_1_iGetDataClearFlag();    // read sample from the ADC    
            break;
        }
    }
    ADCcount[0] = 0;
    loopCount=0;
    while (loopCount<20){
            PRT2DR|=IO_TEST;  //DRIVE P2[0] HIGH
            ADCcount[loopCount]=ADCINCVR_1_iGetData();
            loopCount++;
            PRT2DR &= ~IO_TEST;  //DRIVE P2[0] LOW 
    }

   

 

   

After taking the 20 samples, I am looking for the highest value in the array.

   

 

   

The problem I am running into is that I can only recover the DC offset portion of the wave.

   

To verify the sampling frequency is sufficent, I put an o-scope on the input wave and output of PRT2DR.  I am able to see that sample is being taken at various portions of the sine wave.

   

 

   

Any Ideas?

   

 

   

Vlad

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24 Replies
ETRO_SSN583
Esteemed Contributor

You need this test in the second loop that accumulates the samples -

   

 

   

if(ADCINCVR_1_fIsDataAvailable())

   

 

   

otherwise you are reading a bunch of invalid samples.

   

 

   

But I would suggest you post a project for forum to look at. Note you also

   

do not need to use an array, just test if current value > last value, save new

   

value if it is, and do this over a few samples. Then reset and do again.

   

 

   

    

   

          

   

"File"

   

“Archive Project”

   

    

   

   

          

   

Use Internet Explorer or Firefox to post, Chrome does not seem to work.

   

   

 

   

Regards, Dana.

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Anonymous
Not applicable

3Vpp with 1V bias, that means some portion of the time, the input is clamped to  0V.

   

Would suggest to change the bias so that at no time would be the signal goes below 0. Best is to have it bias in the middle of your ADC range - If you want to use this method.

   

If the signal is a pure sine wave or a wave that you know the crest factor, you can use a diode or a perfect diode circuit and apply the rectified output that to a capacitor. This would give you the peak value of the signal and by scaling with the crest factor would give you the RMS value.

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Anonymous
Not applicable

Another problem is the ADC used can only have a max. sample rate of around 5kSPS. Unless you have a sample and hold circuit, the reading of the ADC may not be what you expected, Most likely as if the signal be thru a low pass filter

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Bob_Marlowe
Expert II

Whenever possible will you please upload the complete project here, there are some settings that may affect the function of your conversion. To do so, use "Designer -> File -> Archive Project" and then attach the resulting file here (DO NOT use chrome, will not work, other browsers are OK).

   

 

   

Bob

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SampathS_11
Moderator
Moderator

 The ADCINCVR is an integrating ATOD convertor. It integrates the input signal before converting it to a digital value.

   

Supposing you have set the resolution of the ADCINCVR to 13 bits. It would integrate the input for 16.384 milliseconds (as per your settings) and do a conversion. Within the 16.384 milliseconds you would have integrated about 63 cycles of your 3840Hz sinewave input. Hence you will get only the DC component for every measurement plus a small noise caused by a portion of a full cycle not completely covered by a measurement.

   

Set the sample window of the ADCINCVR to a fraction of a full cycle of your sinewave. Then you would get better results when measuring the maximum amplitude. The smaller the fraction, the more accurate the maximum amplitude wille be. As always this is a matter of tradeoffs. If you decrease the sample window, you will have to decrease the resolution.  Even at 7-bits resolution, the ADCINCVR will integrate almost a complete cycle of your 3840 Hz input; hence you will need a faster ADC. Have you considered this?

   

Please tell us the resolution at which your are operating the ADCINCVR. And take care to test for data availability in the ADCINCVR before you proceed to read a sample, as suggested by Dana.

   

 

   

Regards,

   

Sampath

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ETRO_SSN583
Esteemed Contributor

Another approach would be to use DAC and Comparator, basically feed Vx

   

into one side of comparator, DAC into other side, and slew DAC values until

   

comparator stops triping from one sample to the next, eg. DAC value is > Vx.

   

Delay DAC to DAC sample update for a few samples of input while monitoring

   

comparator output.

   

 

   

This works if input is fixed in amplitude, otherwise algorithm would have to take

   

care of AM modulation effects. Maybe delay between samples would effectively

   

integrate out the variation if AM is slow changing relative to Vx fundamental frequency.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thank you all for the great ideas. I added the check to see if data is available(thank you Dana), and set the resolution to 7 bit. Sampath, your explanation makes perfect as to why I am only able to see the DC bias. I will be going over the ADCINCVR datasheet to adjust ADC. Would you suggest using a different ADC? Maybe DelSig?

   

 

   

I have attached the project.

   

Thank you

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Bob_Marlowe
Expert II

If you stick to the ADCINC component you ought to change the "CalcTime" which you set to only 1. It should be 180clock-cycles at minimum and shall be expressed in dataclock cycles which is 1/4 of your CPU-clock. Thus it should be set to 45 to 50 be on the safe side. This will give a sample-rate of 21.3 ksps according to the datasheet.

   

 

   

When precision is not the first goal you might use an SAR with 6 bits precision which is far more faster.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

Your column clock is a little high, 3 Mhz, limit is 2.67 Mhz. The datasheet has

   

conflicting info on this, it shows in other statements 8 Mhz.  I will file a CASE to

   

get this clarified.

   

 

   

I see you commented out the delay after mux switching, that should stay in place.

   

There is no setlling time spec, but you could run a quick test bed to get a rough idea

   

of what it needs to be.

   

 

   

You might consider just one routine to handle average, min, max, just to save code

   

and MIPS since most of these involve a 20 iterations loop, put them all in one loop.

   

 

   

Regards, Dana.

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Bob_Marlowe
Expert II

...  additionally when looking into your source I realize that you are wasting a lot of your precious stack space:

   

All variables declared within a function are locals and will be allocated on the stack, and since main() is a function just the rx- and txData + TXTemp + outputstring take 160 bytes off your 256-byte deep stack.

   

Ways out are: declare the vars as "static" or make them globally.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

Bob, I did not think you were a fan of globals -

   

 

   

    

   

          http://www.cypress.com/?docID=41711

   

 

   

Regards, Dana.

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Bob_Marlowe
Expert II

No, I am not. But if I would have hidden that solution you would for sure have posted that,

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

No, I would not have suggested that comment on stack. Or

   

commented on something that was hidden from me.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thank you for the respones, I will be adjusting stack usage as I get closer to the end of the project.

   

I switched to using the SAR6 and I am able to see .1 change in amplitude. With the 3840hz signal, would I be able to optimize the clocks to see a .01 change in amplitude?

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ETRO_SSN583
Esteemed Contributor

First question is do you have to detect peak cycle to cycle, or over many cycles ?

   

 

   

Assuming over mnay cycles -

   

 

   

To accomidate your input signal, 3V, and to have a resolution to .01, you

   

have to set Vrefhi to Vdd, 5V. That means resolution = 5 / .01 = 500 which

   

implies A 9 bit converter. Increasing SAR clock rate does not change resolution

   

in voltage. It is still bound by 5V / 64 = 78 mV/lsb.

   

 

   

Start from scratch. you have a ~ 4 Khz sine. so ;lets desire to oversample at 10 X,

   

then we need A/D to run at 40 KSPS, and 9 bits opr better. From the chart in AN2239

   

we see we cannot get there unless we either relax resolution or speed. If we go to

   

8 bits, thats 19 mV/LSB, tewice your target of .01 ( 10 mV), with a DS2 (second order

   

modulator Delta Sigma, in a 29466).

   

 

   

So I would start there.

   

 

   

Note in your global properties you have Op-Amp bias and A-buff power set to low, I recomend you set these to high.

   

 

   

Another approach is the DAC Comparator approach I mentioned earlier. That can be done to 9 bits

   

but only works for many cycle peak becuse you have to use a SW loop to ascertain value, and

   

you would have to evaluate using C vs ASM to keep the speed up.

   

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Bob_Marlowe
Expert II

Another choice could be to use a PSoC5 which will easily be able to convert and calculate your measurements with your wanted precision and speed.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

Another approach is mixed analog aproach. If you google opamp peak detector there

   

are no shortage of circuits to look at.

   

 

   

Or do, what looks crude, the below peak detector. Basically feed the input to a PGA then into

   

circuit shown, and chareg to peak over some time period, eg. number sine cycles, then A/D

   

drop across diode and Vcap, then Vpk = Vdropdiode + Vcap. Then use an output configed as

   

open drain and turn it on to reset the peak detector. Note use a schotky diode to maximize range,

   

and possibly a smaller cap as only error is bias current into A/D and leakage.

   

 

   

Food for thought. Regards, Dana.

   

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ETRO_SSN583
Esteemed Contributor

Note, the prior approach would allow you to get much higher resolution, as

   

long as you can tolerate the integrating nature of the solution, eg. need to

   

charge over several cycles the cap. Possibly have a resolution of a mV or better.

   

You would have to do an error analysis.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thank you Dana,

   

How do I go about setting the Vref to 5V?

   

Also, what is the effect of changing Op-Amp Bias and A Buff Power?

   

I will give the DelSig method a shot before trying the comparator example.

   

Vlad

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Anonymous
Not applicable

Yeah the Psoc 5 would be nice, maybe on my next project!

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Anonymous
Not applicable

If you wants to measure both the negative and positive half of the wave with a ADC, you should have your waveforem bias at half between the max. and min. range of the ADC. (mostly likely the Vref). But you should have the ADC sample much quicker than your waveform in order to get meaningful result

   

However, as we already suggested, use a diode and a capactior would allow you to get the peak and would not have the limitation of the speed of the ADC, of course there would be some voltage drop accross the diode. You can also search for circuits that use op-amp and diodes which would have better performance.

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ETRO_SSN583
Esteemed Contributor

How do I go about setting the Vref to 5V?

   

 

   

The global resources window, shown below, usulaly found upper left corner Designer.

   

.

   

Also, what is the effect of changing Op-Amp Bias and A Buff Power?

   

 

   

It affects AC response and common mode range of the analog functions.

   

 

   

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SampathS_11
Moderator
Moderator

 Using a DelSig will improve accuracy for sure. If you can tell me your error budget, I can help you choose the ADC speed (integration time).

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ETRO_SSN583
Esteemed Contributor

From the original posting -

   

 

   

The input wave is 3Vpp @ 3840Hz with a DC bias of 1V.

   

 

   

Regards, Dana.

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