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PSoC 5, 3 & 1 MCU

New Contributor



I want to know the IMO in PSoC is turned off completely during sleep or it is switched to a  very low frequency.







6 Replies
Esteemed Contributor

According to this -




and from TRM -


Device components that are involved in Sleep and Watch-
dog operation are the selected 32 kHz clock (external crystal
or internal), the sleep timer, the Sleep bit in the CPU_SCR0
register, the sleep circuit (to sequence going into and com-
ing out of sleep), the bandgap refresh circuit (to periodically
refresh the reference voltage during sleep), and the watch-
dog timer.


The goal of Sleep operation is to reduce average power
consumption as much as possible. The system has a sleep
state that can be initiated under firmware control. In this
state, the CPU is stopped at an instruction boundary and the
24/48 MHz oscillator (IMO), the Flash memory module, and
bandgap voltage reference are powered down. The only
blocks that remain in operation are the 32 kHz oscillator
(external crystal or internal), PSoC blocks clocked from the
32 kHz clock selection, and the supply voltage monitor cir-


Analog PSoC blocks have individual power down settings
that are controlled by firmware, independently of the sleep
state. Continuous time analog blocks may remain in opera-
tion, since they do not require a clock source. Typically,
switched capacitor analog blocks will not operate, since the
internal sources of clocking for these blocks are stopped.




Regards, Dana.

New Contributor

 Thanks Dana for quick response


Again can you explain the meaning of powered down. Are these completely shut down.Then how will PSoC behave  after wake up







Esteemed Contributor

Searching the TRM and Datasheet, precise verbage not there, so


post a tech case at -










“Technical Support”


“Create a Case”




Regards, Dana.

Esteemed Contributor

In this -





some comments -




Startup Requirements


Both the ECO  and IMO experience periods of instability
when they are first started. Therefore, the ECO output is
not used as a source for the internal 32-K clock or as a
reference for the PLL mode of the IMO until it has had
time to stabilize. The IMO experiences a frequency
overshoot when the PLL is first enabled. As a  result, the
CPU clock speed must be lowered when the IMO is
initially switched to PLL mode to prevent the CPU clock
from exceeding its operational limit.


These circumstances require the ECO and IMO PLL mode
to follow a specific startup sequence. The boot.asm meets
this requirement if the appropriate settings (32KSelect =
External  and PLL_Mode = Ext Lock) are selected in the
Global Resources grid in the Device Editor of
PSoC Designer.




Looks like you can examine boot.asm for additional info.




Regards, Dana.

Not applicable

During sleep, IMO is completely turned off. The only clock running is internal low speed oscillator (ILO). 


For details, see "Sleep Sequence" and "Wake up Sequence" section in "Sleep and Watchdog" chapter of TRM. Here is the TRM link for one of the PSoC 1 devices for reference -

Not applicable

Posting Dana's comments - 




rjvb, you see the confusion, the TRM uses "Powered Down" vs "Powered Off",


so thats why the sugestion for the tech case posting.




But I will take you word that "Powered Down" does not mean power to a low power


state, rather it means completely off.




Regards, Dana








Out of curiosity, I searched on internet on what is inferred by reading "power down". It is mostly taken as completely turned off and not bringing down the power. Yes, there is a chance of misinterpretation though.