Announcements
IMPORTANT: Cypress Developer Community is transitioning on October 20th. To learn more and be prepared for this change, check out our latest announcement.
cancel
Showing results for 
Search instead for 
Did you mean: 

PSoC 5, 3 & 1 MCU

WaMa_286156
Contributor II

I am trying to DMA from an SRAM array into a Control Register at a 100khz rate. (See attached project)

I am building under PSoC Creator 4.2, but also tried it under 4.3. Same results either version of Creator.

According to this post (DMA to GPIO ) feeding a clock into DRQ should work at the clock rate.  As you can see from this image here, once started, the DMA keeps transferring at a high rate ( appears to be about 3mhz).  I am sending 4 bytes,  0,1,2,3 out the control register over and over.

I want the DMA to start over automatically, and transfer at the DRQ rate over and over, re-running the array each time.  (The Preserve parameter is set to 1 for this, and it appears to be working.)

dmaShiftreg.jpeg

The Bytes per burst and request per burst are both 1 (from the DMA wizard):

#define DMA_1_BYTES_PER_BURST 1

#define DMA_1_REQUEST_PER_BURST 1

#define DMA_1_SRC_BASE (CYDEV_SRAM_BASE)

#define DMA_1_DST_BASE (CYDEV_PERIPH_BASE)

/* Variable declarations for DMA_1 */

/* Move these variable declarations to the top of the function */

uint8 DMA_1_Chan;

uint8 DMA_1_TD[1];

void DMA_1_Start() {

    /* DMA Configuration for DMA_1 */

    DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,

        HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));

    DMA_1_TD[0] = CyDmaTdAllocate();

    CyDmaTdSetConfiguration(DMA_1_TD[0], 4, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_AUTO_EXEC_NEXT);

    CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)OutData), LO16((uint32)crPulsesOut_Control_PTR));

    CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]);

    CyDmaChEnable(DMA_1_Chan, 1);

}

Can someone help me with this?

0 Likes
1 Solution
Vison_Zhang
Moderator
Moderator

Please change

CyDmaTdSetConfiguration(DMA_1_TD[0], 4, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_AUTO_EXEC_NEXT);

to CyDmaTdSetConfiguration(DMA_1_TD[0], 4, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR);

Auto Next checkbox should not be checked in DMA wizard tool.

View solution in original post

0 Likes
3 Replies
odissey1
Honored Contributor II

WaMa,

Please find example project here

https://www.cypress.com/comment/405831#comment-405831

/odissey1

pastedImage_0.png

0 Likes
Vison_Zhang
Moderator
Moderator

Please change

CyDmaTdSetConfiguration(DMA_1_TD[0], 4, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_AUTO_EXEC_NEXT);

to CyDmaTdSetConfiguration(DMA_1_TD[0], 4, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR);

Auto Next checkbox should not be checked in DMA wizard tool.

View solution in original post

0 Likes
WaMa_286156
Contributor II

The answer by XiaoweiZ_71 is the closest to the original question, So I will give him credit.  The project I included was pretty well hacked up.

  The "correct" answer is 1) do not use CY_DMA_TD_AUTO_EXEC_NEXT (per XiaolweiZ_71). *and* 2) the Serial Shift Register *cannot be used with DMA with more than 8 bits configured in the shift register*  32 bits configured in the shift register with 4 bytes per burst produces 3 "0" byte outputs and 1 byte with data.

   That limitation is *not* an issue, since the goal is to load from an array in memory.   It does allow for running arbitrarily large arrays without interrupting the cpu, which was the goal

What I do not understand is why the DMA loops, without the CY_DMA_TD_AUTO_EXEC_NEXT, but I am not going to obsess over it.

0 Likes