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PSoC 5, 3 & 1 MCU

TaAl_4540371
New Contributor II

How can I make 16bit Full addder by UDB

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1 Solution
MotooTanaka
Esteemed Contributor

Hi,

If I write a 16 bit full adder in verilog it will be something like

    assign { cout, S } = { 1'b0, A } + { 1'b0, B } + { 4'd0, cin } ;

Since I don't have access to my 5LP boards today, following is an idea sketch.

I'm assuming a CY8CKIT-059 for the target board.

Symbol for the verilog full adder

000-symbol.JPG

Verilog

001-verilog.JPG

Schematic

002-schematic.JPG

main.c

=================

#include "project.h"

#include "stdio.h"

#include "tty_utils.h"

void init_hardware(void)

{

    CyGlobalIntEnable; /* Enable global interrupts. */

    tty_init() ;

}

int main(void)

{

    uint16_t a, b, s ;

    int cin, cout ;

 

    init_hardware() ;

 

    splash("UDB 16bit Full addder test") ;

 

    print("Enter A B cin\n") ;

 

    prompt() ;

    for(;;)

    {

        if (get_line()) {

            sscanf(str, "%hd %hd %d", &a, &b, &cin) ;

            A_LSB_Write( a & 0xFF ) ;

            A_MSB_Write((a >> 😎 & 0xFF) ;

            B_LSB_Write( b & 0xFF ) ;

            B_MSB_Write((b >> 😎 & 0xFF) ;

            cin_Write(cin) ;

            s = (S_MSB_Read() << 😎 | S_LSB_Read() ;

            cout = cout_Read() ;

            snprintf(str, STR_BUF_LEN, "%d + %d + %d = ", a, b, cin ) ;

            print(str) ;

            snprintf(str, STR_BUF_LEN, "%d (cout = %d)\n", s, cout) ;

            print(str) ;

            prompt() ;

        }

    }

}

=================

So the good news is that at least this project is build-able,

but the bad news is that I have not tried it by myself.

Your mileage may vary 😉

moto

P.S. On 4-Nov-2019, I had a chance to test the project with CY8CKIT-059

Although I could not afford time to test all patterns, the samples I entered seem to be fine.

NOTE: I even managed to write "addder" for the title to fulfill the request 😜

000-TeraTerm-log.JPG

View solution in original post

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2 Replies
MotooTanaka
Esteemed Contributor

Hi,

If I write a 16 bit full adder in verilog it will be something like

    assign { cout, S } = { 1'b0, A } + { 1'b0, B } + { 4'd0, cin } ;

Since I don't have access to my 5LP boards today, following is an idea sketch.

I'm assuming a CY8CKIT-059 for the target board.

Symbol for the verilog full adder

000-symbol.JPG

Verilog

001-verilog.JPG

Schematic

002-schematic.JPG

main.c

=================

#include "project.h"

#include "stdio.h"

#include "tty_utils.h"

void init_hardware(void)

{

    CyGlobalIntEnable; /* Enable global interrupts. */

    tty_init() ;

}

int main(void)

{

    uint16_t a, b, s ;

    int cin, cout ;

 

    init_hardware() ;

 

    splash("UDB 16bit Full addder test") ;

 

    print("Enter A B cin\n") ;

 

    prompt() ;

    for(;;)

    {

        if (get_line()) {

            sscanf(str, "%hd %hd %d", &a, &b, &cin) ;

            A_LSB_Write( a & 0xFF ) ;

            A_MSB_Write((a >> 😎 & 0xFF) ;

            B_LSB_Write( b & 0xFF ) ;

            B_MSB_Write((b >> 😎 & 0xFF) ;

            cin_Write(cin) ;

            s = (S_MSB_Read() << 😎 | S_LSB_Read() ;

            cout = cout_Read() ;

            snprintf(str, STR_BUF_LEN, "%d + %d + %d = ", a, b, cin ) ;

            print(str) ;

            snprintf(str, STR_BUF_LEN, "%d (cout = %d)\n", s, cout) ;

            print(str) ;

            prompt() ;

        }

    }

}

=================

So the good news is that at least this project is build-able,

but the bad news is that I have not tried it by myself.

Your mileage may vary 😉

moto

P.S. On 4-Nov-2019, I had a chance to test the project with CY8CKIT-059

Although I could not afford time to test all patterns, the samples I entered seem to be fine.

NOTE: I even managed to write "addder" for the title to fulfill the request 😜

000-TeraTerm-log.JPG

View solution in original post

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Len_CONSULTRON
Honored Contributor II

TaAl,

moto's verilog suggestion appears to be an excellent implementation.  I don't have verilog experience so I can't judge it fully.

I've included a simple project with a HW 16-bit adder in the TopDesign.

It is a simple adder with the following features and limitations:

  • 16-bit A and B input buses.  For this design, I used 4 Control register components to load in the A and B values.  You can use 16-bit inputs from other sources if you want.
  • The HW adder uses combinatorial logic.  You can add latched inputs or latched outputs if you need it to sync with other HW components.
  • There is a bit ADD[16].  It is the carry flag bit if you need it.  If you don't you can get rid of the last 3-input OR gate.

Len

Update:  Improved project using LookUp Table (LUT) with the logic for A, B and carryin inputs and S and carryout outputs.

The Application generates random A and B and computes the ADD in HW and in A+B in SW and dumps to a terminal @ 115.2K 8N1.

Len

Len
"Engineering is an Art. The Art of Compromise."
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