GPIOs can provide only 4mA of current and sink 8mA. Can I connect multiple pins to generate a current of more than 4mA.
So, if i want a current of 20mA can I connect 5 pins together to provide this current???
And also when I require 20mA to be sinked can I connect 3 pins together to sink in the current??
I have seen designs that use connected IO-pins to increase current with PSoC1 to 5. Take care, not to exceed the max. power dissipation for a port or a quadrant. Have a look into the datasheet.
Per CY8C55 datasheet you are limited to 20 mA source, 100 mA sink,
per Vddio supply pin, eg. respective GPIO port.
So there is no confusion, when I posted
"Per CY8C55 datasheet you are limited to 20 mA source, 100 mA sink,
per Vddio supply pin, eg. respective GPIO port."
Thats for all pins in that port. So you can parallel to get to that limit, but do not
exceed the port limits (sum of all pin currents, Iol or Ioh).
Yes you can do it. You can try to use the pins of different quadrants so that you will not reach the maximum limit of quadrant's sourcing & sinking capability.
What exactly are you trying to do for 20mA sinking/sourcing?
One other approach is to recognize the min max specs are at a specific
Vol, Voh. Attached typical graphs show you can get 20 mA out of a pin at
other than worst case logic level voltages. Because the graphs are typicals,
use a worst case fudge factor of 50 100% on V. The implication is that
would cover all process and temp variations.
So for 20 mA sink, the typ output V is .3V, so double that for design purposes at
20mA. So can your circuit tolerate a Voh 0f .6V ?
Actually a safer approach, the Vol spec is 8 mA at .6 Vol. From the graph at 8 mA
the typ curve reads ~ .2V (5V Vdd). So the multiplying factor woud be 3. So at
20 mA typ is ~ .4, so use 1.2 V as a worst case Vol at 20 mA.
This approach is better because graphs represent overall device behaviour. Note
the graphs are at 25 degrees C, so a better plan is still plan on paralleling, to cover
margin on temp effects, but you should be able to parallel less pins.
The Voh case a little tougher because the drive has source bulk effect added to its
drive problem, eg. more variation, lower Voh worst case
So in short, parallel pins as best worst case approach, if running out of pins consider