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PSoC 5, 3 & 1 MCU

Anonymous
Not applicable

Does this kit come with an inbuilt buzzer / light intensity monitoring system as is the case with some other kits....

   

 

   

If no, could you please shed light on how to interface a photodiode/light dependent resistor ?

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17 Replies
Anonymous
Not applicable

The CY8CKIT-001 DVK does not come with Buzzer or light intensity detector. The kit comes with 3 PSoC 3 family processor module, 4 Expandable ports, UART level shifter, Bunch of Leds for debugging, min USB connector. You can find out more about this kit here, http://www.cypress.com/?rID=37464

   

The principle behind Photodiode and LDR is very much the same. In both the devices, with increasing light intensity the resistance of the device decreases(current increases). Hence you can put a series impedance and measure the voltage across the series impedance to detect varying light intensity. 

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Anonymous
Not applicable

 sir, can i interface my light sensor tsl235 directly with CY8CKIT-001 DVK .

   

Suggest me how i can interface my tsl235 with this kit

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Bob_Marlowe
Expert II

Since your frequency input from your tsl235 will range from 10Hz to 300kHz i would suggest to do the following:

   

Set up a timer used as a time-base to generate a pulse every second.

   

Set up a counter that counts up all incoming pulses from your sensor (must be able to count up to 300,000 which will need 24 Bits width) Generate interrupt at capture and reload on capture

   

Set up an ISR connected to the counter's Interrupt output set to rising edge

   

Capture with the 1-second pulse the actual count, read captured value within the ISR.

   

 

   

 

   

To fine-tune your system make (measure) y = ax + b to approximate a and b to give you a more exact value.

   

 

   

Happy coding

   

Bob

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ETRO_SSN583
Esteemed Contributor

If you want to make measurements < 1 Hz, which the light sensor is capable

   

of, you cannot use a 1 Hz gate for that, use reciprocal counter technique, reference

   

material attached.

   

 

   

Regards, Dana.

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Bob_Marlowe
Expert II

Sorry, but datasheet of TSL235 says minimum frequency @ E0  (no light) is 10Hz

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ETRO_SSN583
Esteemed Contributor

Sorry, worst case it will have an offset of 10 Hz, typically its < 1 Hz -

   

 

   

   

 

   

This as well shows this -

   

   

Regards, Dana.

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Bob_Marlowe
Expert II

Excuse me, please! I took the shown E0 max value for min.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

No excuses needed.

   

 

   

The spec you are looking at is a 25 C spec. Furthermore they go out of their

   

way to show in multiple graphs performance below 1 Hz. If you want to accomidate

   

2 - 3 sigmas worth of parts you either make the gate period longer or use reciprocal

   

counting techniques. Or just plan on throwing away dynamic range.

   

 

   

Notice this chart does not align with the typ spec either (inconsistant) -

   

 

   

   

 

   

Of course either of us do not have a clue about end application, environment, or use, so

   

all we can do is cover as many bases as possible.

   

 

   

Of course all this is mute as the part is obsolete.

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ETRO_SSN583
Esteemed Contributor

One other small point about using a 1 Hz gate.

   

 

   

If you are measuring a 10 Hz signal, the meaurement at minimum is +/- 1 count,

   

translate a +/- 10% error in reading.

   

 

   

Thats one more reason to use Reciprocal counting techniques at low frequencies/long

   

gate times.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 Bob Marlowe : actually my work is to detect light intensity of different laser and measure its frequency and develop a device which is very sensitive. so i m using TSL235 converter for my work. You replied to select timer and counter block and read captured value within the ISR.

   

m not getting it.

   

can u please send me demo of how to select all these blocks .

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Bob_Marlowe
Expert II

Showing the pricipals...

   

 

   

Bob

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Anonymous
Not applicable

 Bob: i need to do it on PSoC designer. 

   

send me demo for designer regarding my work.

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Bob_Marlowe
Expert II

You are here in PSoC3 forum, that's the reason why you got my example for Creator 2.2.

   

I would suggest, since my example is not a complete project, get a feeling how it is thoght it should work and make it anew for a PSoC 1 chip, although I think that with your performance and precision wanted (and your thoughts to use an analog sensor instead) it could be advisable to insert the PSoC5 processor-module instead. And: if you do not own an ICE-Cube (In-Circuit-Emulator) it will be a bit tough job to debug your project with a PSoC1.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

In this thread is a solution, ap note, to solve problem.

   

 

   

www.cypress.com/

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 Dana, i now understand the use of using reciprocal counter. how can i design this on PSoC designer. actually m not so much comfortable on this tool. help me out by sending its design sample and one more thing since i m making use of a simple photodiode to detect light levels, so it is imp.to modulate the light using filters to make my design more sensitive so it can detect low level light. plz help me out.

   
        
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ETRO_SSN583
Esteemed Contributor

I added one change to project, to insure ISR occured from falling edge of

   

gate gen compare output. Also added was a bunch of descriptive stuff about

   

the design.

   

 

   

Regards, Dana.

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ETRO_SSN583
Esteemed Contributor

One last change, update comments in main.c with below to fix

   

some errors I had in project description.

   

 

   

// This frequency counter is enabled by a simple gate, derived from timer compare output.
// Gate is set up as 1 sec high, 1 sec low, or 2 Hertz. The cycle starts as follows -
//
//         1) Counter period, CounterFreq24, is loaded with 0xFFFFFF, eg full count.
//         2) Gate timer compare out, TimerGateGen16, we will call it gate, goes high, enabling counter.
//         3) Counter counts down at Fx rate, until gate goes low.
//      4) Gate compare goes low, compare output set up to generate an interrupt - edge.
//        5) ISR sets a flag, GateLowFlag, returns.
//        6) In main() GateLowFlag flag is tested, if true, tells main() to service counter
//        7) Counter is stopped, read, reloaded with 0xFFFFFF. stopping counter allows the reload to
//           immeadiatly update counter.
//        😎 Value read is subtracted from 0xFFFFFF (16777215), that result is # counts in 1 sec gate = Hertz
//        9) Value converted to string, written to LCD
//       10) GateLowFlag flag is cleared, counter (CounterFreq24) start API is called. Note because gate is still
//         low for 1 sec, it does not start counting right away until gate goes high.
//
// Notes -
//
//        1) ISR causes no latency as it occurs when gate goes low, disabling counter.
//        2) Gate is 1 sec, could be used as 100 mS to speed up, scale by 10 the reading.
//        3) Gate timer is 1 sec high, 1 sec low, for a 2 sec measurement latency. This
//           can be shorted by changing the period, but keeping compare value same, so duty cycle
//            of gate timer increases, eg. gate high time stays same, but low time shortend.
//        4) Accuracy is limited by internal 24 Mhz clk of PSOC. If you want high accuracy
//           use a precision external clock.
//        5) Accuracy is also a f( frequency ), lower freqs = bigger error. Example if input is 10 Hz,
//           Gate is 1 Hz, there is a minimum count error +/- 1 count, so effectively thats +/-
//         10% error at 10 Hz. Reciprocal counter technique can take care of that.
//        6) The ISR is a C ISR. boot.tpl must be modified in the root project directory to
//            implement the jump vector for interrupt. The interrupt comes from last block in gate timer
//         chain, TimerGateGen16, in this case DBB01, so that jump vector must be modified to "ljmp _yourISRname"
//        7) CounterFreq24 is 24 bit frequency counter, TimerGateGen16 is gate source to drive CounterFreq24 enable,
//           TestFreq16 is a 16 bit timer used to generate a test frequency for debug/measurement, you can eliminate
//         it and its associated code. CompnegISRsignal is a Digital Inverter to produce an ISR on TimerGateGen16
//         compare output -edge.
//        😎 If you need the digital block the DigInv uses to generate ISR on TimerGateGen16 compare output - edge
//         then eliminate it. Set TimerGateGen16 interrupt property to interrupt on Tc, Insert into code that
//         services ISR flag (GateLowFlag) a delay to fix fact Tc out ISR triggers before compare out (gate) falls
//         to low (which disables CounterFreq24 from further counting). Delay would be >=1 clk of TimerGateGen16,
//         which for 1 sec gate, is 1 / 5 Khz = 200 uS to make sure gate, hence CounterFreq24, finishes counting.

   

 

   

Regards, Dana.

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